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name, product name, and ordering part numbering with the prefix “MB”. However, Cypress will
offer these products to new and existing customers with the series name, product name, and
ordering part number with the prefix “CY”.
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About Cypress
Cypress is the leader in advanced embedded system solutions for the world's most innovative
automotive, industrial, smart home appliances, consumer electronics and medical products.
Cypress' microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable,
high-performance memories help engineers design differentiated products and get them to market
first. Cypress is committed to providing customers with the best support and development
resources on the planet enabling them to disrupt markets by creating new product categories in
record time. To learn more, go to
www.cypress.com.
MB91590 Series
FR Family FR81S 32-Bit Microcontroller
This series is Cypress 32-bit microcontroller designed for automotive and industrial control applications. It contains the FR81S CPU
that is compatible with the FR family. The FR81S has a high level performance among the Cypress FR family by enhancing CPU
instruction pipeline and load store processing, and improving internal bus transfer.
It is best suited for application control for automotive.
Features
FR81S CPU Core
32-bit RISC, load/store architecture, pipeline 5-stage
structure
Peripheral Functions
Clock generation (equipped with SSCG function)
Main
Maximum operating frequency:
128 MHz (Source oscillation = 4.0 MHz and 32 multiplied
(PLL clock multiplication system))
It shows maximum CPU frequency of series. The
specification of each part number can be referred in
“Product Lineup” and “Electrical Characteristics.”
oscillation (4MHz)
Sub oscillation (32kHz) or none sub oscillation
PLL multiplication rate : 1 to 32 times
Built-in Program flash memory capacity 2048 + 64KB (series
maximum)
Built-in Data flash memory capacity(WorkFlash) 64KB
Built-in RAM capacity
RAM
Sub RAM (on AHB)
Backup RAM
Main
General-purpose register : 32 bits ×16 sets
16-bit fixed length instructions (basic instruction),
1 instruction per cycle
192KB (Series maximum)
64KB (Series maximum)
8KB
Instructions appropriate to embedded applications
Memory-to-memory
General-purpose ports (5V Pin) : 63
(dual clock products : 61)
2
Included I C pseudo open drain support ports : 4
transfer instruction
Bit processing instruction
Barrel shift instruction etc.
General-purpose ports (3V Pin) : 93
Included
High-level language support instructions
Function
entry/exit instructions
Register content multi-load and store instructions
48 combined external bus interface (For GDC
external memory I/F)
External bus interface
external memory for I/F use
25-bit address, 16-bit data
Power supply voltage fixed to 3.3V
GDC
Bit search instructions
Logical
1 detection, 0 detection, and change-point
detection
overhead during branch process
Branch instructions with delay slot
Reduced
DMA Controller
to 16 channels can be started simultaneously.
2 transfer factors (Internal peripheral request and software)
Up
Register interlock function
Easy
assembler writing
32-bit multiplication : 5 cycles
16-bit multiplication : 3 cycles
A/D converter (successive approximation type)
resolution :
Conversion time :
Level
8/10-bit
The support at the built-in / instruction level of the multiplier
Signed
Signed
32 channels
3μs
External interrupt input: 16 channels
("H" / "L"), or edge detection (rising or falling)
enabled
Interrupt (PC/PS saving)
6
cycles (16 priority levels)
The Harvard architecture allows simultaneous execution of
program and data access.
LIN-UART
channels, ch.2 to ch.7
synchronous mode, LIN-UART mode is selectable.
LIN protocol Revision 2.1 is supported
SPI (Serial Peripheral Interface) supported (synchronous
mode)
Full-duplex double buffering system
LIN synch break detection (linked to the input capture)
Built-in dedicated baud rate generator
DMA transfer support
UART,
6
Instruction compatibility with the FR Family
Built-in memory protection function (MPU)
protection areas can be specified commonly for
instructions and the data.
Control access privilege in both privilege mode and user
mode.
Eight
Built-in FPU (floating point arithmetic)
IEEE754
compliant
Floating-point register 32-bit × 16 sets
San Jose
,
CA 95134-1709
Cypress Semiconductor Corporation
Document Number: 002-04727 Rev. *B
•
198 Champion Court
•
•
408-943-2600
Revised December 1, 2017
MB91590 Series
Multi-function serial communication (built-in
transmission/reception FIFO memory) :
2 channels for MB91F591/2/4/6/7/9
6 channels for MB91F59A/B
< UART (Asynchronous serial interface) >
• Full-duplex double buffering system, 16-byte
transmission FIFO memory, 16-byte reception FIFO
memory
• Parity or no parity is selectable.
• Built-in dedicated baud rate generator
• An external clock can be used as the transfer clock
• Parity, frame, and overrun error detect functions provided
• DMA transfer support
<CSIO (Synchronous serial interface) >
• Full-duplex double buffering system, 16-byte
transmission FIFO memory, 16-byte reception FIFO
memory
• SPI supported; master and slave systems supported; 5 to
9-bit data length can be set.
• Built-in dedicated baud rate generator (Master operation)
• An external clock can be entered. (Slave operation)
• Overrun error detect function is provided
• DMA transfer support
<LIN-UART (Asynchronous Serial Interface for LIN) >
• Full-duplex double buffering system, 16-byte
transmission FIFO memory, 16-byte reception FIFO
memory
• LIN protocol Revision 2.1 supported
• Master and slave systems supported
• Framing error and overrun error detection
• LIN synch break generation and detection; LIN synch
delimiter generation
• Built-in dedicated baud rate generator
• An external clock can be adjusted by the reload counter
• DMA transfer support
< I
2
C >
• ch.0 and ch.1 only supported
• Full-duplex double buffering system, 16-byte
transmission FIFO memory, 16-byte reception FIFO
memory
• Standard mode (Max. 100kbps) / high-speed mode (Max.
400kbps) supported
• DMA transfer supported (for transmission only)
Free-run timer :
× 2 channels (Can select each channel for input
capture, output compare) for MB91F591/2/4/6/7/9
32-bit × 2 channels (LSYN (LIN synch field detection) for
exclusive input capture) for MB91F591/2/4/6/7/9
32-bit × 8 channels (Can select ch.0, 1, 2, and 3 for input
capture, output compare) for MB91F59A/B
32-bit
Input capture :
× 6 channels (linked to the free-run timer) for
MB91F591/2/4/6/7/9
32-bit × 2 channels (linked to the free-run timer) LSYN (LIN
synch field detected) Exclusive for MB91F591/2/4/6/7/9
32-bit × 12 channels (linked to the free-run timer) LSYN
(LIN synch field detected) for MB91F59A/B
32-bit
Output compare : 32-bit × 4 channels (linked to the free-run
timer)
Sound generator : 5 channels
Frequency
and amplitude sequencers provided
Stepping motor controller : 6 channels
8/10-bit
PWM
High current output supported (4 lines × 6 channels)
Can refer back electromotive force using pin-shared A/D
converter
Real-time clock (RTC) (for day, hours, minutes, seconds)
Main/sub
oscillation frequency can be selected for the
operation clock (dual product only)
Calibration: The hardware watchdog for CR oscillation drive
and real-time clock (RTC) for sub clock drive (dual product
only)
The CR oscillation frequency can be trimmed
The main clock to sub clock (dual product only) ratio can
be corrected by setting the real-time clock prescaler
Clock Supervisor
Monitoring
abnormality (damage of crystal etc.) of sub
oscillation (32kHz) (two system clock kinds) of the outside
and main oscillation (4 MHz)
When abnormality is detected, it switches to the CR clock.
Base timer : 2 channels
16-bit
timer
Any of four PWM/PPG/PWC/reload timer functions can be
selected and used
As for the functions of PWC and reload timer, 2 channels of
cascade mode can be used as 32-bit timer.
CAN Controller (C-CAN) : 3 channels
speed : Up to 1Mbps
64-transmission/reception message buffering : 1 channel,
32-transmission/reception message buffering : 2 channels
Transfer
CRC generation
Watchdog timer
Hardware
watchdog
Software watchdog
Up/down counter: 16-bit × 3 channels for MB91F59A/B
PPG : 16-bit × 24 channels
Reload timer :
16-bit
NMI
Interrupt controller
Interrupt request batch read
Multiple
× 4 channels for MB91F591/2/4/6/7/9
16-bit × 8 channels for MB91F59A/B
interrupts from peripherals can be read by a series
of registers.
Document Number: 002-04727 Rev. *B
Page 2 of 174
MB91590 Series
I/O relocation
Peripheral
Built-in
function pins can be reassigned.
Low-power consumption mode
/ Stop / Watch / Sub RUN mode
Stop (power shutdown) / Watch (power shutdown) mode
GDC part self-support power supply
Sleep
Power on reset
Low-voltage detection reset(external low-voltage detection)
Low-voltage detection reset(internal low-voltage detection)
GDC
frequency : 81MHz
resolution of the display which can support : 800 × 480
at the maximum
Screen overlay of five simultaneous layers at the maximum
(window)
Size of the resolution which can be supported varies
depending on color format.
Analog video input (NTSC)
Digital video input (RGB666/555)
YUV input (BT.656)
Video image expansion/reduction /invert function is
supported
RGB Digital output (6-bit × 3)
Built-in 2D rendering engine
The line drawing is supported.
The Bitblt function is supported.
Display list operation is supported
8bpp indirect color
ARGB-1555 direct color
Alpha blending, anti-aliasing
The
Internal/memory
Sprite engine
Equipped with automatic display function when booted
Maximum of 512 sprites are supported
32 special sprites capable of automatic animation are
supported.
The command list execution is supported.
1bpp, 2bpp, 4bpp, 8bpp indirect color
ARGB-1555, RGB-565, ARGB-8888 direct color
The color format for each sprite can be set.
Horizontal invert, Vertical invert
Alpha blending
Built-in memory
• 800KB(MB91F591/2/4/6/7/9)
• 1792KB(MB91F59A/B)
HS-SPI(MB91F59A/B)
Device Package : LQFP-208, HQFP-208*, BGA320,
TEQFP-208*
CMOS 90nm Technology
Power supplies
Power supply
internal 1.2V is generated from 5V/3.3V with the
voltage step-down circuit.
I/O of an external bus and GDC, 3.3V power supply used.
For other I/O, 5V power supply used.
If 2 power supplies are used, they must turn on in the
specified sequence (5V →3.3V).
The
5V/3.3V
*: Under consideration. For detailed information about mount
conditions, contact your sales representative.
Document Number: 002-04727 Rev. *B
Page 3 of 174
MB91590 Series
Contents
1. Product Lineup .................................................................................................................................................................. 5
2. Pin Assignment ............................................................................................................................................................... 11
2.1
Pin Assignment (MB91F591/2/4/6/7/9 Single Clock Product)...................................................................................... 11
2.2
Pin Assignment (MB91F591/2/4/6/7/9 dual Clock Product) ......................................................................................... 12
2.3
Pin Assignment (MB91F59A/B Single Clock Product) ................................................................................................. 13
2.4
Pin Assignment (MB91F59A/B dual Clock Product) .................................................................................................... 14
2.5
Pin Assignment (BGA Product) ................................................................................................................................... 15
3. Pin Description ................................................................................................................................................................ 16
3.1
Pin Description of LQFP-208/TEQFP-208 ................................................................................................................... 16
3.2
MB91F59A/B (BGA320) .............................................................................................................................................. 30
4. I/O Circuit Type ............................................................................................................................................................... 45
5. Handling Precautions ..................................................................................................................................................... 50
5.1
Precautions for Product Design ................................................................................................................................... 50
5.2
Precautions for Package Mounting .............................................................................................................................. 51
5.3
Precautions for Use Environment ................................................................................................................................ 52
6. Handling Devices ............................................................................................................................................................ 53
7. Block Diagram ................................................................................................................................................................. 56
8. Memory Map .................................................................................................................................................................... 58
9. I/O Map ............................................................................................................................................................................. 68
10. Interrupt Vector Table ................................................................................................................................................... 106
11. Electrical Characteristics ............................................................................................................................................. 109
11.1 Absolute Maximum Ratings ....................................................................................................................................... 109
11.2 Recommended Operating Conditions ....................................................................................................................... 111
11.3 DC Characteristics .................................................................................................................................................... 112
11.4 AC Characteristics ..................................................................................................................................................... 119
11.4.1 Main Clock Timing...................................................................................................................................................... 119
11.5 A/D Converter ............................................................................................................................................................ 163
11.5.1 Electrical Characteristics ............................................................................................................................................ 163
11.5.2 Definition of A/D Converter Terms ............................................................................................................................. 164
11.5.3 Notes on Using A/D Converter ................................................................................................................................... 166
11.6 Flash Memory ............................................................................................................................................................ 167
11.6.1 Electrical Characteristics ............................................................................................................................................ 167
11.6.2 Notes .......................................................................................................................................................................... 167
12. Ordering Information .................................................................................................................................................... 168
13. Package Dimensions .................................................................................................................................................... 169
14. Major Changes .............................................................................................................................................................. 172
Document History ............................................................................................................................................................... 173
Sales, Solutions, and Legal Information........................................................................................................................... 174
Products .............................................................................................................................................................................. 174
PSoC
®
Solutions ................................................................................................................................................................. 174
Cypress Developer Community......................................................................................................................................... 174
Technical Support .............................................................................................................................................................. 174
Document Number: 002-04727 Rev. *B
Page 4 of 174
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