71321SA35JG datasheet, PDF - EEWORLD Datasheet

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71321SA35JG: DescriptionDual-Port SRAM, 2KX8, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52; Categorystorage; File Size140KB，17 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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71321SA35JG Overview

Dual-Port SRAM, 2KX8, 35ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52

71321SA35JG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	LCC
package instruction	QCCJ, LDCC52,.8SQ
Contacts	52
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	35 ns
Other features	AUTOMATIC POWER DOWN
I/O type	COMMON
JESD-30 code	S-PQCC-J52
JESD-609 code	e3
length	19.1262 mm
memory density	16384 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of ports	2
Number of terminals	52
word count	2048 words
character code	2000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	2KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC52,.8SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum standby current	0.015 A
Minimum standby current	4.5 V
Maximum slew rate	0.165 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	19.1262 mm
Base Number Matches	1

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HIGH SPEED

2K X 8 DUAL-PORT

STATIC RAM

WITH INTERRUPTS

Features

◆

IDT71321SA/LA

IDT71421SA/LA

◆

High-speed access

– Commercial: 20/25/35/55ns (max.)

– Industrial: 25/55ns (max.)

Low-power operation

– IDT71321/IDT71421SA

—

Active: 325mW (typ.)

—

Standby: 5mW (typ.)

– IDT71321/421LA

—

Active: 325mW (typ.)

—

Standby: 1mW (typ.)

Two

INT

flags for port-to-port communications

◆

MASTER IDT71321 easily expands data bus width to 16-or-

more-bits using SLAVE IDT71421

On-chip port arbitration logic (IDT71321 only)

BUSY

output flag on IDT71321;

BUSY

input on IDT71421

Fully asynchronous operation from either port

Battery backup operation – 2V data retention (LA only)

TTL-compatible, single 5V ±10% power supply

Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Functional Block Diagram

R/W

I/O

- I/O

I/O

Control

BUSY

10L

(1,2)

I/O

Control

I/O

-I/O

BUSY

Address

Decoder

(1,2)

MEMORY

ARRAY

Address

Decoder

10R

R/W

ARBITRATION

and

INTERRUPT

LOGIC

R/W

INT

(2)

INT

2691 drw 01

(2)

NOTES:

1. IDT71321 (MASTER):

BUSY

is open drain output and requires pullup resistor of 270Ω.

IDT71421 (SLAVE):

BUSY

is input.

2. Open drain output: requires pullup resistor of 270Ω.

OCTOBER 2008

DSC-2691/13

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