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FIN3383MTD

Description
Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
CategoryAnalog mixed-signal IC    Drivers and interfaces   
File Size549KB,18 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
Download Datasheet Parametric Compare View All

FIN3383MTD Overview

Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers

FIN3383MTD Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeTSSOP
package instruction6.10 MM, MO-153, TSSOP-56
Contacts56
Reach Compliance Codeunknow
ECCN codeEAR99
Differential outputYES
Number of drives4
Input propertiesSTANDARD
Interface integrated circuit typeLINE DRIVER
Interface standardsEIA-644; TIA-644
JESD-30 codeR-PDSO-G56
JESD-609 codee3
length14 mm
Humidity sensitivity level2
Number of functions4
Number of terminals56
Maximum operating temperature70 °C
Minimum operating temperature-10 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP56,.3,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
Maximum receive delay
Maximum seat height1.1 mm
Maximum slew rate66 mA
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width6.1 mm
FIN3385 • FIN3383 • FIN3384 • FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
October 2003
Revised April 2005
FIN3385 • FIN3383 •
FIN3384 • FIN3386
Low Voltage 28-Bit Flat Panel Display Link
Serializers/Deserializers
General Description
The FIN3385 and FIN3383 transform 28 bit wide parallel
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 28 bits of input LVTTL data are sampled and trans-
mitted.
The FIN3386 and FIN3384 receive and convert the 4/3
serial LVDS data streams back into 28/21 bits of LVTTL
data. Refer to Table 1 for a matrix summary of the Serializ-
ers and Deserializers available. For the FIN3385, at a
transmit clock frequency of 85MHz, 28 bits of LVTTL data
are transmitted at a rate of 595Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and cable
size problems associated with wide and high-speed TTL
interfaces.
Features
s
Low power consumption
s
20 MHz to 85 MHz shift clock support
s
r
1V common-mode range around 1.2V
s
Narrow bus reduces cable size and cost
s
High throughput (up to 2.38 Gbps throughput)
s
Internal PLL with no external component
s
Compatible with TIA/EIA-644 specification
s
Devices are offered 56-lead TSSOP packages
Ordering Code:
Order Number
FIN3383MTD
FIN3384MTD
FIN3385MTD
FIN3386MTD
Package Number
MTD56
MTD56
MTD56
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
TABLE 1. Display Panel Link Serializers/Deserializers Chip Matrix
Part
FIN3385
FIN3383
FIN3386
FIN3384
CLK Frequency
85
66
85
66
LVTTL IN
28
28
LVDS OUT
4
4
4
4
28
28
LVDS IN
LVTTL OUT
Package
56 TSSOP
56 TSSOP
56 TSSOP
56 TSSOP
© 2005 Fairchild Semiconductor Corporation
DS500864
www.fairchildsemi.com

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