FIN3385 • FIN3383 • FIN3384 • FIN3386 Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
October 2003
Revised April 2005
FIN3385 • FIN3383 •
FIN3384 • FIN3386
Low Voltage 28-Bit Flat Panel Display Link
Serializers/Deserializers
General Description
The FIN3385 and FIN3383 transform 28 bit wide parallel
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 28 bits of input LVTTL data are sampled and trans-
mitted.
The FIN3386 and FIN3384 receive and convert the 4/3
serial LVDS data streams back into 28/21 bits of LVTTL
data. Refer to Table 1 for a matrix summary of the Serializ-
ers and Deserializers available. For the FIN3385, at a
transmit clock frequency of 85MHz, 28 bits of LVTTL data
are transmitted at a rate of 595Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and cable
size problems associated with wide and high-speed TTL
interfaces.
Features
s
Low power consumption
s
20 MHz to 85 MHz shift clock support
s
r
1V common-mode range around 1.2V
s
Narrow bus reduces cable size and cost
s
High throughput (up to 2.38 Gbps throughput)
s
Internal PLL with no external component
s
Compatible with TIA/EIA-644 specification
s
Devices are offered 56-lead TSSOP packages
Ordering Code:
Order Number
FIN3383MTD
FIN3384MTD
FIN3385MTD
FIN3386MTD
Package Number
MTD56
MTD56
MTD56
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
TABLE 1. Display Panel Link Serializers/Deserializers Chip Matrix
Part
FIN3385
FIN3383
FIN3386
FIN3384
CLK Frequency
85
66
85
66
LVTTL IN
28
28
LVDS OUT
4
4
4
4
28
28
LVDS IN
LVTTL OUT
Package
56 TSSOP
56 TSSOP
56 TSSOP
56 TSSOP
© 2005 Fairchild Semiconductor Corporation
DS500864
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FIN3385 • FIN3383 • FIN3384 • FIN3386
Block Diagrams
Functional Diagram for FIN3385 and FIN3383
Receiver Functional Diagram for FIN3386 and FIN3384
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2
FIN3385 • FIN3383 • FIN3384 • FIN3386
TRANSMITTERS
Pin Descriptions
Pin Names
TxIn
TxCLKIn
TxOut
TxOut
TxCLKOut
TxCLKOut
R_FB
PwrDn
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
V
CC
GND
NC
I/O Type Number of Pins
I
I
O
O
O
O
I
I
I
I
I
I
I
I
28/21
1
4/3
4/3
1
1
1
1
1
2
1
3
3
5
Description of Signals
LVTTL Level Input
LVTTL Level Clock Input
The rising edge is for data strobe.
Positive LVDS Differential Data Output
Negative LVDS Differential Data Output
Positive LVDS Differential Clock Output
Negative LVDS Differential Clock Output
Rising Edge Clock (HIGH), Falling Edge Clock (LOW)
LVTTL Level Power-Down Input
Assertion (LOW) puts the outputs in High Impedance state.
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pin for LVDS Output
Ground Pins for LVDS Output
Power Supply Pins for LVTTL Input
Ground pins for LVTTL Input
No Connect
Connection Diagram
FIN3383 and FIN3385 (28:4 Transmitter)
Pin Assignment for TSSOP
Truth Table
Inputs
TxIn
Active
Active
F
F
X
TxCLKIn
Active
L/H/Z
Active
F
X
PwrDn
(Note 1)
H
H
H
H
L
Outputs
TxOut
r
L/H
L/H
L
L
Z
TxCLKOut
r
L/H
X (Note 2)
L/H
X (Note 2)
Z
H HIGH Logic Level
L LOW Logic Level
X Don’t Care
Z High Impedance
F Floating
Note 1:
The outputs of the transmitter or receiver will remain in a
High Impedance state until V
CC
reaches 2V.
Note 2:
TxCLKOut
r
will settle at a free running frequency when the
part is powered up, PwrDn is HIGH and the TxCLKIn is a steady logic
level (L/H/Z).
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FIN3385 • FIN3383 • FIN3384 • FIN3386
RECEIVERS
Pin Descriptions
Pin Names I/O Type
RxIn
RxIn
RxCLKIn
RxCLKIn
RxOut
RxCLKOut
PwrDn
PLL V
CC
PLL GND
LVDS V
CC
LVDS GND
V
CC
GND
NC
I
I
I
I
O
O
I
I
I
I
I
I
I
Number
of Pins
4/3
4/3
1
1
28/21
1
1
1
2
1
3
4
5
Description of Signals
Negative LVDS Differential Data Input
Positive LVDS Differential Data Input
Negative LVDS Differential Clock Input
Positive LVDS Differential Clock Input
LVTTL Level Data Output
Goes HIGH for PwrDn LOW
LVTTL Clock Output
LVTTL Level Input
Refer to Transmitter and Receiver Power-Up and Power-Down Operation Truth Table
Power Supply Pin for PLL
Ground Pins for PLL
Power Supply Pin for LVDS Input
Ground Pins for LVDS Input
Power Supply for LVTTL Output
Ground Pin for LVTTL Output
No Connect
Connection Diagram
FIN3386 and FIN3384 (4:28 Receiver)
Pin Assignment for TSSOP
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4
FIN3385 • FIN3383 • FIN3384 • FIN3386
Transmitter and Receiver Power-Up/Power-Down Operation Truth Table
The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. The following table
shows the operation of the transmitter during power-up and power-down and operation of the PwrDn pin.
Transmitter
V
CC
TxIn
TxOut
TxCLKIn
TxCLKOut
r
PwrDn
Receiver
RxIn
r
RxOut
RxCLKIn
r
RxCLKOut
PwrDn
V
CC
H HIGH Logic Level
L LOW Logic Level
P Last Valid State
X Don’t Care
Z High-Impedance
PwrDn
Normal
2V
X
Z
X
Z
L
X
Z
X
Z
L
!
2V
X
Z
X
Z
L
PwrDn
X
L
X
(Note 5)
L
!
2V
Active
Active
Active
Active
H
Active
L/H
Active
Active
H
!
2V
Active
X
H/L/Z
(Note 3)
H
Active
P
(Note 4)
(Note 5)
H
!
2V
!
2V
H
(Note 4)
H
Active
(Note 5)
H
H
(Note 4)
P
(Note 4)
(Note 5)
H
2V
2V
2V
2V
2V
2V
Note 3:
If the transmitter is powered up and PwrDn is inactive HIGH and the clock input goes to any state LOW, HIGH, or Z then the internal PLL will go to a
known low frequency and stay until the clock starts normal operation again.
Note 4:
If the input is terminated and un-driven (Z) or shorted or open. (fail safe condition)
Note 5:
For PwrDn or fail safe condition the RxCLKOut pin will go LOW for Panel Link devices and HIGH for Channel Link devices.
Note 6:
Shorted here means (
r
inputs are shorted to each other, or
r
inputs are shorted to each other and Ground or V
CC
, or either
r
inputs are shorted to
Ground or V
CC
) with no other Current/Voltage sources (noise) applied. If the V
ID
is still in the valid range (greater than 100mV) and VCM is in the valid range
(0V to 2.4V) then the input signal is still recognized and the part will respond normally.
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