935278794115 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> logic> 935278794115

935278794115: DescriptionNAND Gate, AHC/VHC/H/U/V Series, 4-Func, 2-Input, CMOS, PQCC14; Categorylogic logic; File Size119KB，17 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

Download Datasheet Parametric Compare View All

935278794115 Overview

NAND Gate, AHC/VHC/H/U/V Series, 4-Func, 2-Input, CMOS, PQCC14

935278794115 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nexperia
package instruction	HVQCCN,
Reach Compliance Code	compliant
series	AHC/VHC/H/U/V
JESD-30 code	R-PQCC-N14
JESD-609 code	e4
length	3 mm
Logic integrated circuit type	NAND GATE
Humidity sensitivity level	1
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	HVQCCN
Package shape	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
propagation delay (tpd)	19.5 ns
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
width	2.5 mm
Base Number Matches	1

Preview

Download Datasheet

View All

74AHC132; 74AHCT132

Quad 2-input NAND Schmitt trigger

Rev. 06 — 4 May 2009

Product data sheet

1. General description

The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard

No. 7-A.

The 74AHC132; 74AHCT132 contains four 2-input NAND gates which accept standard

input signals. They are capable of transforming slowly changing input signals into sharply

deﬁned, jitter free output signals. The gate switches at different points for positive-going

and negative-going signals. The difference between the positive voltage V

T+

and the

negative V

T−

is deﬁned as the hysteresis voltage V

2. Features

Balanced propagation delays

Inputs accept voltages higher than V

Input levels:

For 74AHC132: CMOS level

For 74AHCT132: TTL level

ESD protection:

HBM EIA/JESD22-A114E exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

CDM EIA/JESD22-C101C exceeds 1000 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and from

−40 °C

to +125

°C

3. Ordering information

Table 1.

Ordering information

Package

Temperature range Name

74AHC132

74AHC132D

74AHC132PW

74AHC132BQ

−40 °C

to +125

°C

−40 °C

to +125

°C

−40 °C

to +125

°C

SO14

TSSOP14

plastic small outline package; 14 leads;

body width 3.9 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT108-1

SOT402-1

SOT762-1

Description

Version

Type number

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5

0.85 mm

935278794115 Related Products

	935278794115	935262991118	74AHC132PW	74AHC132D	74AHC132BQ
Description	NAND Gate, AHC/VHC/H/U/V Series, 4-Func, 2-Input, CMOS, PQCC14	NAND Gate, AHC/VHC/H/U/V Series, 4-Func, 2-Input, CMOS, PDSO14	NAND Gate, AHC/VHC/H/U/V Series, 4-Func, 2-Input, CMOS, PDSO14	NAND Gate, AHC/VHC/H/U/V Series, 4-Func, 2-Input, CMOS, PDSO14	NAND Gate, AHC/VHC/H/U/V Series, 4-Func, 2-Input, CMOS, PQCC14
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to
Maker	Nexperia	Nexperia	Nexperia	Nexperia	Nexperia
package instruction	HVQCCN,	TSSOP,	TSSOP,	SOP,	HVQCCN,
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant
series	AHC/VHC/H/U/V	AHC/VHC/H/U/V	AHC/VHC/H/U/V	AHC/VHC/H/U/V	AHC/VHC/H/U/V
JESD-30 code	R-PQCC-N14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PQCC-N14
JESD-609 code	e4	e4	e4	e4	e4
length	3 mm	5 mm	5 mm	8.65 mm	3 mm
Logic integrated circuit type	NAND GATE	NAND GATE	NAND GATE	NAND GATE	NAND GATE
Humidity sensitivity level	1	1	1	1	1
Number of functions	4	4	4	4	4
Number of entries	2	2	2	2	2
Number of terminals	14	14	14	14	14
Maximum operating temperature	125 °C	125 °C	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVQCCN	TSSOP	TSSOP	SOP	HVQCCN
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
propagation delay (tpd)	19.5 ns	19.5 ns	19.5 ns	19.5 ns	19.5 ns
Maximum seat height	1 mm	1.1 mm	1.1 mm	1.75 mm	1 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2 V	2 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	NO LEAD	GULL WING	GULL WING	GULL WING	NO LEAD
Terminal pitch	0.5 mm	0.65 mm	0.65 mm	1.27 mm	0.5 mm
Terminal location	QUAD	DUAL	DUAL	DUAL	QUAD
width	2.5 mm	4.4 mm	4.4 mm	3.9 mm	2.5 mm
Base Number Matches	1	1	1	1	1
Peak Reflow Temperature (Celsius)	-	-	260	260	260
Certification status	-	-	Not Qualified	Not Qualified	Not Qualified
Maximum time at peak reflow temperature	-	-	30	30	30

Recommended Resources

Pass the weak magnetic field through a high-gain amplifier that amplifies it 1000 times

Bedside lamp safety switch circuit (2)

Three-dial combination electronic lock circuit

Resistor combination lock circuit

Simple music lantern controller circuit

Noise and noise filter circuit diagram

Some basic methods for reading mobile phone circuit diagrams: Many students and colleagues have reported that they have replaced all the components of a faulty mobile phone, but the phone still cannot be repaired. In most cases, they do not have a thorough under...; fighting Analog electronics

RS flip-flop and D flip-flop: RS flip-flop and D flip-flop...; Analog electronics

Comparison of current measurement circuits on SAM L21 xplained and EFM32 development boards: I will post the diagram first, and then write the circuit analysis. The diagram is a bit large, click on the image to enlarge it. SAM L21EFM32...; dcexpert Microchip MCU

I don't know if selling posts is illegal. I want to sell the zigbee module. I only did a graduation project once, so it's 99% new.: Only used once, almost new, with all kinds of information, please contact QQ372138862 if you need it...; csjiuxin Buy&Sell

Excellent filter design software: [i=s]This post was last edited by paulhyde on 2014-9-15 03:10[/i] This should be of great help to students who design filters!!!...; W1Z1Q Electronics Design Contest

Show the process of WEBENCH design + CPU power design: The WEBENCH design box that will appear after entering TI's official website 1. Select FPGA/UP here, and click UP design2. After entering the design page, select the CPU model to be designed,Here, AM3...; dontium Analogue and Mixed Signal

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components