EEWORLDEEWORLDEEWORLD

Part Number

Search

74AC373PCX

Description
Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDIP20, 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-20
Categorylogic   
File Size105KB,10 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Download Datasheet Parametric View All

74AC373PCX Overview

Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDIP20, 0.300 INCH, LEAD FREE, PLASTIC, MS-001, DIP-20

74AC373PCX Parametric

Parameter NameAttribute value
MakerFairchild
Parts packaging codeDIP
package instructionDIP,
Contacts20
Reach Compliance Codeunknown
seriesAC
JESD-30 codeR-PDIP-T20
length25.905 mm
Logic integrated circuit typeBUS DRIVER
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)15 ns
Certification statusNot Qualified
Maximum seat height5.33 mm
Maximum supply voltage (Vsup)6 V
Minimum supply voltage (Vsup)2 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm
Base Number Matches1
74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs
November 1988
Revised November 1999
74AC373 • 74ACT373
Octal Transparent Latch with 3-STATE Outputs
General Description
The AC/ACT373 consists of eight latches with 3-STATE
outputs for bus organized system applications. The flip-
flops appear transparent to the data when Latch Enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the bus
output is in the high impedance state.
Features
s
I
CC
and I
OZ
reduced by 50%
s
Eight latches in a single package
s
3-STATE outputs for bus interfacing
s
Outputs source/sink 24 mA
s
ACT373 has TTL-compatible inputs
Ordering Code:
Order Number
74AC373SC
74AC373SJ
74AC373MTC
74AC373PC
74ACT373SC
74ACT373SJ
74ACT373MSA
74ACT373MTC
74ACT373PC
Package Number
M20B
M20D
MTC20
N20A
M20B
M20D
MSA20
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering information
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009958
www.fairchildsemi.com
[Award Ceremony] Vishay Automotive Electronics Theme Month Winners List Announced!
Activity details: Win big prizes by passing the VISHAY Automotive Electronics Theme Month! Activity link: [url=https://www.eeworld.com.cn/Vishay/2012_activity/Automotive/]https://www.eeworld.com.cn/Vi...
EEWORLD社区 Discrete Device
How to add relative path of header file in ccs?
First, under Project->Properties->Build, click Variables to add a variable, then you can use ${} to reference the variable under Project->Properties->Build->C2000 Compiler->Include Options. The system...
Aguilera Microcontroller MCU
Circuit
Why is the voltage obtained on R1 of the boards made in these two pictures different?...
hql724914 PCB Design
Can Gigabit Ethernet be implemented in the XC5VLX50 chip of XILINX V5?
In this series of chips, there is no built-in MAC, no ROCKET IO, etc. Can we use external integrated MAC+PHY chips and V5 chip IO pins to achieve Gigabit Ethernet? In short, can this chip achieve Giga...
eeleader FPGA/CPLD
Is my chip broken?
Why is the USART DR register always zero when I send data? {:1_122:}...
大家都是好朋友 stm32/stm8
Different types of pin headers
Could you please tell me what the naming convention is for pin headers? Common 2.54mm pitch HDR, what does HDR mean? The 1.27 seems to be MHDR, the 5.08 seems to be HDRX, what is the 2.0mm one?...
sfcsdc PCB Design

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1840  311  2480  880  2063  38  7  50  18  42 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号