Am50DL9608G
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
27025
Revision
A
Amendment
+4
Issue Date
May 19, 2003
PRELIMINARY
Am50DL9608G
Stacked Multi-Chip Package (MCP) Flash Memory and Pseudo SRAM
64 Megabit (4 M x 16-Bit) and 32 Megabit (2 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories, and
8 Mbit (512 K x 16-Bit) Pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
■
Power supply voltage of 2.7 to 3.3 volt
■
High performance
— Flash access time as fast as 70 ns
— Pseudo SRAM access time as fast as 55 ns
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate function
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
Package
— 73-Ball FBGA
■
Minimum 1 million erase cycles guaranteed per sector
■
20 year data retention at 125°C
— Reliable operation for the life of the system
■
Operating Temperature
— –40°C to +85°C
SOFTWARE FEATURES
■
Supports Common Flash Memory Interface (CFI)
■
Program/Erase Suspend/Erase Resume
— Suspends program/erase operations to allow
programming/erasing in same bank
Flash Memory Features
(Am29DL640G/Am29DL320G)
— Features apply to Am29DL640G and Am29DL320G
independently.
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
■
Flexible Bank architecture
— Read may occur in any of the three banks not being written
or erased.
— Four banks may be grouped by customer to achieve desired
bank divisions.
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
the read mode
■
Manufactured on 0.17 µm process technology
■
SecSi™ (Secured Silicon) Sector
— Extra 256 byte sector on Am29DL640G
— Extra 256 byte sector on Am29DL320G
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
—
Customer lockable:
Sector is one-time programmable.
Once sector is locked, data cannot be changed.
■
WP#/ACC input pin
— Write protect (WP#) protects sectors 0, 1, 140, and 141 in
Am29DL640G, and two outermost boot sectors in
Am29DL320G
— Acceleration (ACC) function accelerates program timing
■
Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
■
Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
■
Boot sectors
— Top and bottom boot sectors in Am29DL640G
— Top or bottom boot options in Am29DL320G
Pseudo SRAM Features
■
Power dissipation
— Operating: 30 mA maximum
— Standby: 60 µA maximum
■
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
■
CE1s# and CE2s Chip Select
■
Power down features using CE1s# and CE2s
■
Data retention supply voltage: 2.7 to 3.3 volt
■
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
PERFORMANCE CHARACTERISTICS
■
High performance
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice. 5/19/03
Publication#
27025
Rev:A Amendment/+4
Issue Date:
May 19, 2003
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am50DL9608G consists of two flash memory de-
vices (one 64-Mbit Am29DL640G and one 32-Mbit
Am29DL320G), and one 8 Mbit pseudo SRAM device.
Bottom boot configuration is shown in the following ta-
ble.
Bank
Bank 1
Bank 2
Bank 3
Bank 4
Megabits
4 Mb
12 Mb
12 Mb
4 Mb
Sector Sizes
Eight 32 Kword
Twenty-four 32 Kword
Twenty-four 32 Kword
Eight 4 Kword,
Seven 32 Kword
Am29DL640G and Am29DL320G Features
Am29DL640G is a 64 megabit, 3.0 volt-only flash
memory device, organized as 4,194,304 words. The
Am29DL320G is a 32 megabit, 3.0 volt-only flash
memory device, organized as 2,097,152 words. Word
mode data appears on DQ15–DQ0. The device is de-
signed to be programmed in-system with the standard
3.0 volt V
CC
supply, and can also be programmed in
standard EPROM programmers.
The device is available with an access time of 70 or 85
ns and is offered in a 73-ball FBGA package. Standard
control pins—chip enable (CE#fx), write enable
(WE#), and output enable (OE#)—control normal read
and write operations, and avoid bus contention issues.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
Available on Am29DL640G and Am29DL320G, the
SecSi™ (Secured Silicon) Sector
is an extra 256
byte sector capable of being permanently locked by
AMD or customers. The Secure SectorSecSi
Indica-
tor Bit
(DQ7) is permanently set to a 1 if the part is
factory locked,
and set to a 0 if
customer lockable.
This way, customer lockable parts can never be used
to replace a factory locked part.
Factory locked parts provide several options. The Se-
cure SectorSecSi Sector may store a secure, random
16 byte ESN (Electronic Serial Number), customer
code (programmed through AMD’s ExpressFlash ser-
vice), or both. Customer Lockable parts may utilize the
Secure SectorSecSi Sector as a one-time program-
mable area.
The AMD
DMS (Data Management Software)
man-
ages data programming, enables EEPROM emulation,
and eases historical sector erase flash limitations. For
more information on DMS or to obtain the software,
contact AMD or an authorized representative.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into
four banks.
Sector addresses are fixed,
system software can be used to form user-defined
bank groups.
During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can im-
prove overall system performance by allowing a host
system to program or erase in one bank, then
immediately and simultaneously read from the other
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.
The Am29DL640G can be organized as both a top
and bottom boot sector configuration.
Bank
Bank 1
Bank 2
Bank 3
Bank 4
Megabits
8 Mb
24 Mb
24 Mb
8 Mb
Sector Sizes
Eight 4 Kword,
Fifteen 32 Kword
Forty-eight 32 Kword
Forty-eight 32 Kword
Eight 4 Kword,
Fifteen 32 Kword
The Am29DL320G can be organized as either a top or
bottom boot sector configuration. Top boot configura-
tion is shown in the following table.
Bank
Bank 1
Bank 2
Bank 3
Bank 4
Megabits
4 Mb
12 Mb
12 Mb
4 Mb
Sector Sizes
Eight 4 Kword,
Seven 32 Kword
Twenty-four 32 Kword
Twenty-four 32 Kword
Eight 32 Kword
2
Am50DL9608G
May 19, 2003
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
MCP Device Bus Operations . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations—Flash Word Mode .................... 10
Figure 5. Erase Operation.............................................................. 37
Erase Suspend/Erase Resume Commands ........................... 37
Table 22. Am29DL640G and Am29DL320G Command Definitions 38
Flash Write Operation Status . . . . . . . . . . . . . . . 39
DQ7: Data# Polling ................................................................. 39
Figure 6. Data# Polling Algorithm .................................................. 39
DQ6: Toggle Bit I .................................................................... 40
Figure 7. Toggle Bit Algorithm........................................................ 40
Flash Device Bus Operations . . . . . . . . . . . . . . . 11
Requirements for Reading Array Data ................................... 11
Writing Commands/Command Sequences ............................ 11
Simultaneous Read/Write Operations with Zero Latency ....... 11
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Pin ............................................... 12
Output Disable Mode .............................................................. 12
Table 2. Am29DL640G Sector Architecture ....................................13
Table 3. Am29DL640G Bank Address ............................................16
Table 4. Am29DL640G SecSi Sector Addresses .......................16
Table 5. Am29DL320G Top Boot Sector Addresses .....................17
Table 6. Am29DL320G Top Boot SecSi
TM
Sector Addresses ........ 18
Table 7. Am29DL320G Bottom Boot Sector Addresses .................19
Table 8. Am29DL320G Bottom Boot SecSi
TM
Sector Addresses ... 20
Table 9. Am29DL640G Boot Sector/Sector Block
Addresses for Protection/Unprotection ...........................................21
Table 10. Am29DL320G Top Boot Sector/Sector
Block Addresses for Protection/Unprotection ..................................22
Table 11. Am29DL320G Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................22
DQ2: Toggle Bit II ................................................................... 41
Reading Toggle Bits DQ6/DQ2 ............................................... 41
DQ5: Exceeded Timing Limits ................................................ 41
DQ3: Sector Erase Timer ....................................................... 41
Table 23. Write Operation Status ................................................... 42
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 43
Figure 8. Maximum Negative Overshoot Waveform ...................... 43
Figure 9. Maximum Positive Overshoot Waveform........................ 43
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 44
CMOS Compatible ..................................................................... 44
Figure 10. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 45
Figure 11. Typical I
CC1
vs. Frequency ............................................ 45
Pseudo SRAM DC and
Operating Characteristics . . . . . . . . . . . . . . . . . . 46
Figure 12. Standby Current ISB CMOS ......................................... 46
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13. Test Setup.................................................................... 47
Figure 14. Input Waveforms and Measurement Levels ................. 47
Write Protect (WP#) ................................................................ 23
Table 12. WP#/ACC Modes ............................................................23
Flash AC Characteristics . . . . . . . . . . . . . . . . . . 48
Pseudo SRAM CE#s Timing ...................................................... 48
Figure 15. Timing Diagram for Alternating
Between Pseudo SRAM to Flash................................................... 48
Temporary Sector Unprotect .................................................. 23
Figure 1. Temporary Sector Unprotect Operation........................... 24
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 25
Read-Only Operations .............................................................. 49
Figure 16. Read Operation Timings ............................................... 49
SecSi™ (Secured Silicon) Sector
SectorFlash Memory Region ................................................. 26
Table 13. SecSi Sector Programming ................................................26
Figure 3. SecSi Sector Protect Verify.............................................. 27
Hardware Reset (RESET#) ....................................................... 50
Figure 17. Reset Timings ............................................................... 50
Erase and Program Operations ................................................. 51
Figure 18. Program Operation Timings..........................................
Figure 19. Accelerated Program Timing Diagram..........................
Figure 20. Chip/Sector Erase Operation Timings ..........................
Figure 21. Back-to-back Read/Write Cycle Timings ......................
Figure 22. Data# Polling Timings (During Embedded Algorithms).
Figure 23. Toggle Bit Timings (During Embedded Algorithms)......
Figure 24. DQ2 vs. DQ6.................................................................
52
52
53
54
54
55
55
Hardware Data Protection ...................................................... 27
Common Flash Memory Interface (CFI) . . . . . . . 27
Table 14. Am29DL640G CFI Query Identification String ................ 28
Table 15. Am29DL640G System Interface String ........................... 28
Table 16. Am29DL640G Device Geometry Definition..................... 29
Table 17. Am29DL640G Primary Vendor-Specific
Extended Query .............................................................................. 30
Table 18. Am29DL320G CFI Query Identification String ................ 31
Table 19. Am29DL320G System Interface String ........................... 31
Table 20. Am29DL320G Device Geometry Definition..................... 32
Table 21. Am29DL320G Primary Vendor-Specific
Extended Query .............................................................................. 33
Temporary Sector Unprotect ..................................................... 56
Figure 25. Temporary Sector Unprotect Timing Diagram .............. 56
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 57
Alternate CE#f Controlled Erase and Program Operations ....... 58
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 59
Flash Command Definitions . . . . . . . . . . . . . . . . 34
Reading Array Data ................................................................ 34
Reset Command ..................................................................... 34
Autoselect Command Sequence ............................................ 34
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 34
Program Command Sequence ............................................... 35
Figure 4. Program Operation .......................................................... 36
Pseudo SRAM AC Characteristics . . . . . . . . . . . 60
Power Up Time .......................................................................... 60
Read Cycle ................................................................................ 60
Figure 28. Pseudo SRAM Read Cycle—Address Controlled......... 60
Figure 29. Pseudo SRAM Read Cycle........................................... 61
Write Cycle ................................................................................ 62
Figure 30. Pseudo SRAM Write Cycle—WE# Control ................... 62
Figure 31. Pseudo SRAM Write Cycle—CE1#s Control ................ 63
Figure 32. Pseudo SRAM Write Cycle—
Chip Erase Command Sequence ........................................... 36
Sector Erase Command Sequence ........................................ 36
May 19, 2003
Am50DL9608G
3
P R E L I M I N A R Y
UB#s and LB#s Control................................................................... 64
Flash Erase And Programming Performance . . . 65
Latchup Characteristics . . . . . . . . . . . . . . . . . . . 65
BGA Package Capacitance . . . . . . . . . . . . . . . . 65
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . 65
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 66
FTA073—73-Ball Fine-Pitch Grid Array 8 x 11.6 mm ................ 66
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 67
4
Am50DL9608G
May 19, 2003
Analogue and Mixed Signal
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