Am41DL16x4D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
25562
Revision
A
Amendment
0
Issue Date
October 24, 2001
PRELIMINARY
Am41DL16x4D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29DL16xD 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous
Operation Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
s
Power supply voltage of 2.7 to 3.3 volt
s
High performance
— Access time as fast as 70 ns
SOFTWARE FEATURES
s
Data Management Software (DMS)
— AMD-supplied software manages data programming and
erasing, enabling EEPROM emulation
— Eases sector erase limitations
s
Package
— 69-Ball FBGA
s
Supports Common Flash Memory Interface (CFI)
s
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in same
bank
s
Operating Temperature
— –40°C to +85°C
Flash Memory Features
ARCHITECTURAL ADVANTAGES
s
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
s
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
s
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
s
Any combination of sectors can be erased
s
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
s
Secured Silicon (SecSi) Sector: Extra 64 KByte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function.
—
Customer lockable:
Can be read, programmed, or erased
just like other sectors. Once locked, data cannot be changed
s
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
reading array data
s
Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero
s
WP#/ACC input pin
— Write protect (WP#) function allows protection of two outermost
boot sectors, regardless of sector protect status
— Acceleration (ACC) function accelerates program timing
s
Top or bottom boot block
s
Manufactured on 0.23 µm process technology
s
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
s
Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
PERFORMANCE CHARACTERISTICS
s
High performance
— 70 ns access time
— Program time: 4 µs/word typical utilizing Accelerate function
SRAM Features
s
Power dissipation
— Operating: 22 mA maximum
— Standby: 10 µA maximum
s
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
s
Minimum 1 million write cycles guaranteed per sector
s
20 Year data retention at 125°C
— Reliable operation for the life of the system
s
s
s
s
CE1#s and CE2s Chip Select
Power down features using CE1#s and CE2s
Data retention supply voltage: 1.5 to 3.3 volt
Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 25562 Rev:
A
Amendment/0
Issue Date:
October 24, 2001
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
Am29DL16xD Features
The Am29DL16xD family is a 16 megabit, 3.0 volt-only
flash memory device, organized as 1,048,576 words of
16 bits or 2,097,152 bytes of 8 bits each. Word mode
data appears on DQ15–DQ0; byte mode data ap-
pears on DQ7–DQ0. The device is designed to be
programmed in-system with the standard 3.0 volt V
CC
supply, and can also be programmed in standard
EPROM programmers.
The device is available with access times of 70 ns or
85 ns. The device is offered in a 69-ball FBGA pack-
age. Standard control pins—chip enable (CE#f), write
enable (WE#), and output enable (OE#)—control nor-
m a l re a d a nd write op e rat ion s, a nd avo id b us
contention issues.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
reading and writing like any other flash sector, or may
permanently lock their own code there.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is a n a d v a n t a g e c o m p a re d to sy st e m s w h e re
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and
software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
o r y. T h i s c a n b e a c h i e v e d i n - s y s t e m o r v i a
programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
Th e system can also place the de vice into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and
simultaneously read from the other bank, with zero la-
tency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DL16xD devices uses multiple bank archi-
tectures to provide flexibility for different applications.
Four devices are available with the following bank
sizes:
Device
DL161
DL162
DL163
DL164
Bank 1
0.5 Mb
2 Mb
4 Mb
8 Mb
Bank 2
15.5 Mb
14 Mb
12 Mb
8 Mb
The
Secured Silicon (SecSi) Sector
is an extra 64
Kbit sector capable of being permanently locked by
AMD or customers. The
SecSi Sector Indicator Bit
(DQ7) is permanently set to a 1 if the part is
factory
locked,
and set to a 0 if
customer lockable.
This
way, customer lockable parts can never be used to re-
place a factory locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number). Customer Lockable
parts may utilize the SecSi Sector as bonus space,
2
Am41DL16x4D
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5
Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions for FBGA Package .................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
SRAM Word Mode, CIOs = V
CC
..................................................... 11
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
SRAM Byte Mode, CIOs = V
SS
......................................................12
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SS
;
SRAM Word Mode, CIOs = V
CC
.....................................................13
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
; SRAM
Byte Mode, CIOs = V
SS
..................................................................14
Reading Array Data ................................................................ 26
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 27
Byte/Word Program Command Sequence ............................. 27
Unlock Bypass Command Sequence .................................. 27
Figure 3. Program Operation ......................................................... 28
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 29
Figure 4. Erase Operation.............................................................. 29
Table 16. Command Definitions (Flash Word Mode) ...................... 30
Table 17. Autoselect Device IDs (Word Mode) .............................. 30
Table 18. Command Definitions (Flash Byte Mode) ....................... 31
Table 19. Autoselect Device IDs (Byte Mode) ............................... 31
Write Operation Status . . . . . . . . . . . . . . . . . . . . 32
DQ7: Data# Polling ................................................................. 32
Figure 5. Data# Polling Algorithm .................................................. 32
Word/Byte Configuration ....................................................... 15
Requirements for Reading Array Data ................................... 15
Writing Commands/Command Sequences ............................ 15
Accelerated Program Operation .......................................... 15
Autoselect Functions ........................................................... 15
Simultaneous Read/Write Operations with Zero Latency ....... 15
Standby Mode ........................................................................ 16
Automatic Sleep Mode ........................................................... 16
RESET#: Hardware Reset Pin ............................................... 16
Output Disable Mode .............................................................. 16
Table 5. Device Bank Division ........................................................16
Table 6. Sector Addresses for Top Boot Sector Devices ............... 17
Table 7. SecSi Sector Addresses for Top Boot Devices ................17
Table 8. Sector Addresses for Bottom Boot Sector Devices ...........18
Table 9. SecSi Addresses for Bottom Boot Devices ..................18
RY/BY#: Ready/Busy# ............................................................ 33
DQ6: Toggle Bit I .................................................................... 33
Figure 6. Toggle Bit Algorithm........................................................ 33
DQ2: Toggle Bit II ................................................................... 34
Reading Toggle Bits DQ6/DQ2 ............................................... 34
DQ5: Exceeded Timing Limits ................................................ 34
DQ3: Sector Erase Timer ....................................................... 34
Table 20. Write Operation Status ................................................... 35
Autoselect Mode ..................................................................... 19
Table 10. Top Boot Sector/Sector Block Addresses for Protection/Un-
protection ........................................................................................19
Table 11. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................19
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 36
Industrial (I) Devices ............................................................ 36
V
CC
f/V
CC
s Supply Voltage ................................................... 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37
CMOS Compatible .................................................................. 37
SRAM DC and Operating Characteristics . . . . . 38
Zero-Power Flash ................................................................. 39
Figure 9. I
CC1
Current vs. Time (Showing Active and Automatic Sleep
Currents) ........................................................................................ 39
Figure 10. Typical I
CC1
vs. Frequency ............................................ 39
Write Protect (WP#) ................................................................ 19
Temporary Sector/Sector Block Unprotect ............................. 20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-
rithms .............................................................................................. 21
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Test Setup.................................................................... 40
Table 21. Test Specifications ......................................................... 40
Key To Switching Waveforms . . . . . . . . . . . . . . . 40
Figure 12. Input Waveforms and Measurement Levels ................. 40
SecSi (Secured Silicon) Sector Flash Memory Region .......... 22
Factory Locked: SecSi Sector Programmed and Protected At
the Factory .......................................................................... 22
Customer Lockable: SecSi Sector NOT Programmed or Pro-
tected At the Factory ........................................................... 22
Hardware Data Protection ...................................................... 22
Low V
CC
Write Inhibit ........................................................... 22
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Common Flash Memory Interface (CFI) . . . . . . . 23
Table 12. CFI Query Identification String........................................ 23
System Interface String................................................................... 24
Table 14. Device Geometry Definition ............................................ 24
Table 15. Primary Vendor-Specific Extended Query ...................... 25
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41
SRAM CE#s Timing ................................................................ 41
Figure 13. Timing Diagram for Alternating Between
SRAM to Flash ............................................................................... 41
Flash Read-Only Operations ................................................. 42
Figure 14. Read Operation Timings ............................................... 42
Hardware Reset (RESET#) .................................................... 43
Figure 15. Reset Timings ............................................................... 43
Flash Word/Byte Configuration (CIOf) .................................... 44
Figure 16. CIOf Timings for Read Operations................................ 44
Figure 17. CIOf Timings for Write Operations................................ 44
Flash Erase and Program Operations .................................... 45
Figure 18. Program Operation Timings..........................................
Figure 19. Accelerated Program Timing Diagram..........................
Figure 20. Chip/Sector Erase Operation Timings ..........................
Figure 21. Back-to-back Read/Write Cycle Timings ......................
46
46
47
48
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Am41DL16x4D
3
P R E L I M I N A R Y
Figure 22. Data# Polling Timings (During Embedded Algorithms).. 48
Figure 23. Toggle Bit Timings (During Embedded Algorithms)....... 49
Figure 24. DQ2 vs. DQ6.................................................................. 49
Figure 31. SRAM Write Cycle—CE1#s Control ............................. 57
Figure 32. SRAM Write Cycle—UB#s and LB#s Control ............... 58
Temporary Sector/Sector Block Unprotect ............................. 50
Figure 25. Temporary Sector/Sector Block Unprotect
Timing Diagram............................................................................... 50
Figure 26. Sector/Sector Block Protect and Unprotect
Timing Diagram............................................................................... 51
Flash Erase And Programming Performance .
Flash Latchup Characteristics. . . . . . . . . . . . . . .
Package Pin Capacitance . . . . . . . . . . . . . . . . . .
FLASH Data Retention . . . . . . . . . . . . . . . . . . . . .
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . .
59
59
59
59
60
Alternate CE#f Controlled Erase and Program Operations .... 52
Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-
eration Timings................................................................................ 53
Figure 33. CE1#s Controlled Data Retention Mode....................... 60
Figure 34. CE2s Controlled Data Retention Mode......................... 60
SRAM Read Cycle .................................................................. 54
Figure 28. SRAM Read Cycle—Address Controlled....................... 54
Figure 29. SRAM Read Cycle ......................................................... 55
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 61
FLA069—69-Ball Fine-Pitch Grid Array 8 x 11 mm ............... 61
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 62
Revision A (October 24, 2001) ............................................... 62
SRAM Write Cycle .................................................................. 56
Figure 30. SRAM Write Cycle—WE# Control ................................. 56
4
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