EEWORLDEEWORLDEEWORLD

Part Number

Search

531KC802M000DGR

Description
CMOS/TTL Output Clock Oscillator, 802MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
Categoryoscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531KC802M000DGR Overview

CMOS/TTL Output Clock Oscillator, 802MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531KC802M000DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability7%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency802 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage1.89 V
Minimum supply voltage1.71 V
Nominal supply voltage1.8 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
The problem of failure to program the new CC2530 board
I'm working on a CC2530 board recently, but I can't program the new board. I can't detect the chip with SmartRF Flash Programmer. I initially suspected that the 2530 chip was not soldered properly, bu...
heliset RF/Wirelessly
【Keysight Essay Call】My Story with Agilent Oscilloscopes
[i=s]This post was last edited by weijinke on 2017-3-31 14:35[/i] [align=left][align=left]The first time I heard about Agilent oscilloscopes was when I was in college. I used Multisim to do digital ci...
weijinke Test/Measurement
Could you please tell me where the problem is in the following program? Thanks for your help.
modulexiyi(QP,cp,MUSIC,k,zheng,fan,rst,CLK,BCD1,BCD2,Segout, SG1,SG2,SG3,SG4,SG5,SG6); input k,rst; input cp; input [7:0]QP; input CLK; input [3:0]BCD1,BCD2; output [6:0]Segout; output SG1,SG2,SG3,SG4...
nickylam FPGA/CPLD
EEWORLD University - Guide to Electronic Information Science and Technology
Introduction to Electronic Information Science and Technology : https://training.eeworld.com.cn/course/4106...
老白菜 Analog electronics
Please recommend a programmable voltage-stabilized power supply that meets the following requirements.
I need a programmable voltage-stabilized power supply with the following requirements: Multi-channel (≥4) output voltage up to 24V/current up to 1A; Programmable, open API, preferring our software pro...
suoma Power technology
CAN bus basic knowledge and standard specifications
For friends who want to learn about CAN bus, this document is available for download and study. CAN bus is a rapidly developing field bus and is currently widely used in industrial automation, ships, ...
mcq1989 Industrial Control Electronics

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1556  2625  982  1422  264  32  53  20  29  6 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号