Am29LV002B
Data Sheet
The Am29LV002B is not offered for new designs. Please contact a Spansion representative for alter-
nates.
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro and
changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number
21520
Revision
D
Amendment
5
Issue Date
October 11, 2006
THIS PAGE LEFT INTENTIONALLY BLANK.
DATA SHEET
Am29LV002B
2 Megabit (256 K x 8-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
The Am29LV002B is not offered for new designs. Please contact a Spansion representative for alternates.
DISTINCTIVE CHARACTERISTICS
■
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■
Manufactured on 0.32 µm process technology
— Compatible with 0.5 µm Am29LV002 device
■
High performance
— Full voltage range: access times as fast as 70 ns
— Regulated voltage range: access times as fast as
55 ns
■
Ultra low power consumption (typical values at 5
MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
■
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
three 64 Kbyte sectors
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that
sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Unlock Bypass Mode Program Command
— Reduces overall programming time when issuing
multiple program command sequences
■
Top or bottom boot block configurations
available
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Minimum 1,000,000 write cycle guarantee per
sector
■
20-year data retention at 125°C
— Reliable operation for the life of the system
■
Package option
— 40-pin TSOP
■
Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■
Data# Polling and toggle bits
— Provides a software method of detecting program
or erase operation completion
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication#
21520
Rev:
D
Amendment:
5
Issue Date:
October 11, 2006
DATA SHEET
GENERAL DESCRIPTION
The Am29LV002B is an 2 Mbit, 3.0 volt-only Flash
memory organized as 262,144 bytes. The device is
offered in a 40-pin TSOP package. The byte-wide (x8)
data appears on DQ7–DQ0. This device requires only a
single, 3.0 volt VCC supply to perform read, program,
and erase operations. A standard EPROM programmer
can also be used to program and erase the device.
This device is manufactured using AMD’s 0.32 µm
process technology, and offers all the features and ben-
efits of the Am29LV002, which was manufactured using
0 . 5 µ m p r o c e s s t e c h n o l o gy. I n a d d i t i o n , t h e
Am29LV002B features unlock bypass programming
and in-system sector protection/unprotection.
The standard device offers access times of 55, 70, 90,
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The
Unlock Bypass
mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the
Embedded
Erase
algorithm—an internal algorithm that automati-
cally preprograms the array (if it is not already
programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
2
Am29LV002B
21520D5 October 11, 2006
DATA SHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 10
Table 1. Am29LV002B Device Bus Operations .............................. 10
Reading Toggle Bits DQ6/DQ2 ............................................... 21
Figure 6. Toggle Bit Algorithm ........................................................ 22
DQ5: Exceeded Timing Limits ................................................ 22
DQ3: Sector Erase Timer ....................................................... 22
Table 6. Write Operation Status..................................................... 23
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 24
Figure 7. Maximum Negative Overshoot Waveform ...................... 24
Figure 8. Maximum Positive Overshoot Waveform ........................ 24
Requirements for Reading Array Data ................................... 10
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 11
Standby Mode ........................................................................ 11
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Am29LV002BT Top Boot Block Sector Address Table..... 12
Table 3. Am29LV002BB Bottom Boot Block Sector Address Table 12
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 9. I
CC1
Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 26
Figure 10. Typical I
CC1
vs. Frequency ........................................... 26
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 11. Test Setup ..................................................................... 27
Table 7. Test Specifications ........................................................... 27
Figure 12. Input Waveforms and Measurement Levels ................. 27
Autoselect Mode ..................................................................... 12
Table 4. Am29LV002B Autoselect Codes (High Voltage Method).. 12
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Operations .................................................................... 28
Figure 13. Read Operations Timings ............................................. 28
Sector Protection/Unprotection ............................................... 13
Temporary Sector Unprotect .................................................. 13
Hardware Data Protection ...................................................... 13
Figure 1. Temporary Sector Unprotect Operation ...........................13
Hardware Reset (RESET#) .................................................... 29
Figure 14. RESET# Timings .......................................................... 29
Erase/Program Operations ..................................................... 30
Figure 15. Program Operation Timings .......................................... 31
Figure 16. Chip/Sector Erase Operation Timings .......................... 32
Figure 17. Data# Polling Timings (During Embedded Algorithms) . 33
Figure 18. Toggle Bit Timings (During Embedded Algorithms) ...... 33
Figure 19. DQ2 vs. DQ6 ................................................................. 34
Low V
CC
Write Inhibit .............................................................. 13
Write Pulse “Glitch” Protection ............................................... 13
Logical Inhibit .......................................................................... 13
Power-Up Write Inhibit ............................................................ 13
Figure 2. In-System Sector Protect/Unprotect Algorithms ...............14
Temporary Sector Unprotect .................................................. 34
Figure 20. Temporary Sector Unprotect Timing Diagram .............. 34
Figure 21. Sector Protect/Unprotect Timing Diagram .................... 35
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 15
Reading Array Data ................................................................ 15
Reset Command ..................................................................... 15
Autoselect Command Sequence ............................................ 15
Byte Program Command Sequence ....................................... 15
Unlock Bypass Command Sequence ..................................... 16
Chip Erase Command Sequence ........................................... 16
Figure 3. Program Operation ..........................................................16
Alternate CE# Controlled Erase/Program Operations ............ 36
Figure 22. Alternate CE# Controlled Write Operation Timings ...... 37
Sector Erase Command Sequence ........................................ 17
Erase Suspend/Erase Resume Commands ........................... 17
Figure 4. Erase Operation ...............................................................18
Command Definitions ............................................................. 19
Table 5. Am29LV002B Command Definitions................................. 19
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 20
DQ7: Data# Polling ................................................................. 20
Figure 5. Data# Polling Algorithm ...................................................20
RY/BY#: Ready/Busy# ........................................................... 21
DQ6: Toggle Bit I .................................................................... 21
DQ2: Toggle Bit II ................................................................... 21
Erase and Programming Performance . . . . . . . 38
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 39
TS 040—40-Pin Standard TSOP* .......................................... 39
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 40
Revision A (January 1998) ..................................................... 40
Revision B (June 1998) .......................................................... 40
Revision B+1 (August 1998) ................................................... 40
Revision C (January 1999) ..................................................... 40
Revision D (November 18, 1999) ........................................... 40
Revision D+1 (November 13, 2000) ....................................... 40
Revision D+2 (June 14, 2004) ................................................ 40
Revision D+3 (January 5, 2006) ............................................. 40
Revision D+4 (September 12, 2006) ...................................... 40
21520D5 October 11, 2006
Am29LV002B
3
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