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3D3418-0.25

Description
MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3418 - LOW NOISE)
Categorylogic    logic   
File Size161KB,7 Pages
ManufacturerData Delay Devices
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3D3418-0.25 Overview

MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D3418 - LOW NOISE)

3D3418-0.25 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerData Delay Devices
Parts packaging codeDIP
package instructionDIP,
Contacts16
Reach Compliance Codecompliant
Input frequency maximum value (fmax)6.25 MHz
JESD-30 codeR-PDIP-T16
length19.305 mm
Logic integrated circuit typeSILICON DELAY LINE
Number of functions1
Number of taps/steps255
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
programmable delay lineYES
Certification statusNot Qualified
Maximum seat height4.58 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Total delay nominal (td)83.25 ns
width7.62 mm
Base Number Matches1
3D3418
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D3418 – LOW NOISE)
FEATURES
PACKAGES
All-silicon, low-power 3.3V CMOS technology
1
VDD
IN
16
Vapor phase, IR and wave solderable
2
OUT
AE
15
Auto-insertable (DIP pkg.)
3
MD
SO/P0
14
Low ground bounce noise
IN
1
16
4
P7
P1
13
AE
2
15
Leading- and trailing-edge accuracy
SO/P0
3
14
5
P6
P2
12
Increment range:
0.25 through 7.5ns
P1
4
13
6
SC
P3
11
P2
5
12
Delay tolerance:
1% (See Table 1)
P3
6
11
7
P5
P4
10
P4
7
10
Temperature stability:
±3%
typical (0C-70C)
GND
8
9
Vdd stability:
±1%
typical (3.0V-3.6V)
8
SI
GND
9
3D3418S SOL
Static Idd:
1.3ma typical
3D3418 DIP
(300 Mil)
Minimum input pulse width:
10% of total
3D3418G Gull Wing
delay
Programmable via 3-wire serial or 8-bit parallel interface
For mechanical dimensions, click
here
.
VDD
OUT
MD
P7
P6
SC
P5
SI
FUNCTIONAL DESCRIPTION
The 3D3418 Programmable 8-Bit Silicon Delay Line product family
consists of 8-bit, user-programmable CMOS silicon integrated
circuits. Delay values, programmed either via the serial or parallel
interface, can be varied over 255 equal steps ranging from 250ps
to 7.5ns inclusively. Units have a typical inherent (address 0)
delay of 20ns (See Table 1). The input is reproduced at the output
without inversion, shifted in time as per user selection. The
3D3418 is CMOS-compatible, and features both rising- and
falling-edge accuracy.
PIN DESCRIPTIONS
IN
OUT
MD
AE
P0-P7
SC
SI
SO
VDD
GND
Signal Input
Signal Output
Mode Select
Address Enable
Parallel Data Input
Serial Clock
Serial Data Input
Serial Data Output
+3.3 Volts
Ground
The all-CMOS 3D3418 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL programmable delay lines. It is offered in a standard 16-pin
auto-insertable DIP and a space saving surface mount 16-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D3418-0.25
3D3418-0.5
3D3418-1
3D3418-2
3D3418-3
3D3418-4
3D3418-5
3D3418-7.5
DELAYS AND TOLERANCES
Step 0
Delay (ns)
19.5
±
3.0
19.5
±
3.0
19.5
±
3.0
20.0
±
3.5
20.0
±
3.5
20.0
±
3.5
20.0
±
3.5
20.5
±
3.5
Step 255
Delay (ns)
83.25
±
4.0
147.0
±
4.0
274.5
±
5.0
530.0
±
6.0
785.0
±
8.0
1040
±
9.0
1295
±
10
1933
±
15
Delay
Increment (ns)
0.25
±
0.15
0.50
±
0.25
1.00
±
0.50
2.00
±
1.00
3.00
±
1.50
4.00
±
2.00
5.00
±
2.50
7.50
±
3.75
Max Operating
Frequency
6.25 MHz
3.15 MHz
1.56 MHz
0.78 MHz
0.52 MHz
0.39 MHz
0.31 MHz
0.21 MHz
INPUT RESTRICTIONS
Absolute Max
Oper Freq
90 MHz
45 MHz
22 MHz
11 MHz
7.5 MHz
5.5 MHz
4.4 MHz
2.9 MHz
Min Operating
P.W.
80.0 ns
160.0 ns
320.0 ns
640.0 ns
960.0 ns
1280.0 ns
1600.0 ns
2400.0 ns
Absolute Min
Oper P.W.
5.5 ns
11.0 ns
22.0 ns
44.0 ns
66.0 ns
88.0 ns
110.0 ns
165.0 ns
NOTES: Any delay increment between 0.25 and 7.5 ns not shown is also available.
All delays referenced to input pin
2002
Data Delay Devices
Doc #02006
10/28/02
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1

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Is it lead-free? Contains lead - Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead Contains lead
Is it Rohs certified? incompatible - incompatible incompatible incompatible incompatible incompatible incompatible incompatible
Maker Data Delay Devices - Data Delay Devices Data Delay Devices Data Delay Devices Data Delay Devices Data Delay Devices Data Delay Devices Data Delay Devices
Parts packaging code DIP - DIP DIP DIP DIP DIP DIP DIP
package instruction DIP, - DIP, DIP, DIP, DIP, DIP, DIP, DIP,
Contacts 16 - 16 16 16 16 16 16 16
Reach Compliance Code compliant - compliant compliant compliant compliant compliant compliant compliant
Input frequency maximum value (fmax) 6.25 MHz - 3.15 MHz 1.56 MHz 0.78 MHz 0.52 MHz 0.21 MHz 0.39 MHz 0.31 MHz
JESD-30 code R-PDIP-T16 - R-PDIP-T16 R-PDIP-T16 R-PDIP-T16 R-PDIP-T16 R-PDIP-T16 R-PDIP-T16 R-PDIP-T16
length 19.305 mm - 19.305 mm 19.305 mm 19.305 mm 19.305 mm 19.305 mm 19.305 mm 19.305 mm
Logic integrated circuit type SILICON DELAY LINE - SILICON DELAY LINE SILICON DELAY LINE SILICON DELAY LINE SILICON DELAY LINE SILICON DELAY LINE SILICON DELAY LINE SILICON DELAY LINE
Number of functions 1 - 1 1 1 1 1 1 1
Number of taps/steps 255 - 255 255 255 255 255 255 255
Number of terminals 16 - 16 16 16 16 16 16 16
Maximum operating temperature 70 °C - 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
Output polarity TRUE - TRUE TRUE TRUE TRUE TRUE TRUE TRUE
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP - DIP DIP DIP DIP DIP DIP DIP
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE - IN-LINE IN-LINE IN-LINE IN-LINE IN-LINE IN-LINE IN-LINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
programmable delay line YES - YES YES YES YES YES YES YES
Certification status Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 4.58 mm - 4.58 mm 4.58 mm 4.58 mm 4.58 mm 4.58 mm 4.58 mm 4.58 mm
Maximum supply voltage (Vsup) 3.6 V - 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3 V - 3 V 3 V 3 V 3 V 3 V 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount NO - NO NO NO NO NO NO NO
technology CMOS - CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level COMMERCIAL - COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form THROUGH-HOLE - THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
Terminal pitch 2.54 mm - 2.54 mm 2.54 mm 2.54 mm 2.54 mm 2.54 mm 2.54 mm 2.54 mm
Terminal location DUAL - DUAL DUAL DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Total delay nominal (td) 83.25 ns - 147 ns 274.5 ns 530 ns 785 ns 1933 ns 1040 ns 1295 ns
width 7.62 mm - 7.62 mm 7.62 mm 7.62 mm 7.62 mm 7.62 mm 7.62 mm 7.62 mm
Base Number Matches 1 - 1 1 1 1 1 1 1
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