AM29DL320GB30EF datasheet, PDF

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AM29DL320GB30EF: Description2M X 16 FLASH 3V PROM, 70 ns, PDSO48; Categorystorage; File Size768KB，58 Pages; ManufacturerAMD; Websitehttp://www.amd.com

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AM29DL320GB30EF Overview

2M X 16 FLASH 3V PROM, 70 ns, PDSO48

AM29DL320GB30EF Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	48
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	2.7 V
Rated supply voltage	3 V
maximum access time	70 ns
Processing package description	TSOP-48
state	TRANSFERRED
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	SMALL OUTLINE, THIN PROFILE
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
Terminal location	DUAL
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
memory width	16
organize	2M X 16
storage density	3.36E7 deg
operating mode	ASYNCHRONOUS
Number of digits	2.10E6 words
Number of digits	2M
Spare memory width	8
Memory IC type	FLASH 3V PROM
serial parallel	PARALLEL

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Am29DL320G

Data Sheet

RETIRED

PRODUCT

This product has been retired and is not recommended for designs. For new and current designs,

S29JL032H (for TSOP packages) and S29PL032J (for FBGA packages) supersede AM29DL320G as

the factory-recommended migration path. Please refer to each respective datasheets for specifica-

tions and ordering information. Availability of this document is retained for reference and historical

purposes only.

April 2005

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that

originally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appro-

priate, and changes will be noted in a revision summary.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Publication Number

25769

Revision

Amendment

Issue Date

May 25, 2005

TABLE OF CONTENTS

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Special Package Handling Instructions .......................................... 6

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 1. Device Bus Operations .............................................................9

Sector Erase Command Sequence .............................................. 26

Erase Suspend/Erase Resume Commands ................................ 27

Figure 5. Erase Operation .................................................................... 27

Table 13. Command Definitions ........................................................... 28

DQ7: Data# Polling ...................................................................... 29

Figure 6. Data# Polling Algorithm ......................................................... 29

Word/Byte Configuration ................................................................ 9

Requirements for Reading Array Data ........................................... 9

Writing Commands/Command Sequences .................................. 10

Simultaneous Read/Write Operations

with Zero Latency .........................................................................10

Standby Mode .............................................................................. 10

Automatic Sleep Mode .................................................................10

RESET#: Hardware Reset Pin .....................................................11

Output Disable Mode ...................................................................11

Table 2. Top Boot Sector Addresses ...................................................12

Table 3. Top Boot SecSi

Sector Addresses ..................................... 13

Table 4. Bottom Boot Sector Addresses ...............................................14

Table 5. Bottom Boot SecSi

Sector Addresses ................................ 15

RY/BY#: Ready/Busy# ................................................................. 30

DQ6: Toggle Bit I .......................................................................... 30

Figure 7. Toggle Bit Algorithm .............................................................. 30

DQ2: Toggle Bit II ......................................................................... 31

Reading Toggle Bits DQ6/DQ2 .................................................... 31

DQ5: Exceeded Timing Limits ...................................................... 31

DQ3: Sector Erase Timer ............................................................. 31

Table 14. Write Operation Status ......................................................... 32

Figure 8. Maximum Negative Overshoot Waveform............................. 33

Figure 9. Maximum Positive Overshoot Waveform .............................. 33

Figure 10. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents).................................................................... 35

Figure 11. Typical I

CC1

vs. Frequency................................................... 35

Figure 12. Test Setup .......................................................................... 36

Figure 13. Input Waveforms and Measurement Levels ........................ 36

Figure 14. Read Operation Timings...................................................... 37

Figure 15. Reset Timings...................................................................... 38

Autoselect Mode .......................................................................... 16

Table 6. Autoselect Codes, (High Voltage Method) .............................16

Sector/Sector Block Protection and Unprotection ........................ 17

Table 7. Top Boot Sector/Sector Block Addresses

for Protection/Unprotection ...................................................................17

Table 8. Bottom Boot Sector/Sector Block Addresses

for Protection/Unprotection ...................................................................17

Word/Byte Configuration (BYTE#) ............................................... 39

Figure 16. BYTE# Timings for Read Operations .................................. 39

Figure 17. BYTE# Timings for Write Operations .................................. 39

Write Protect (WP#) .....................................................................18

Temporary Sector Unprotect ........................................................18

Figure 1. Temporary Sector Unprotect Operation................................. 18

Figure 2. In-System Sector Protection/

Sector Unprotection Algorithms ............................................................ 19

Erase and Program Operations ................................................... 40

Figure 18. Program Operation Timings ................................................

Figure 19. Accelerated Program Timing Diagram ................................

Figure 20. Chip/Sector Erase Operation Timings .................................

Figure 21. Back-to-back Read/Write Cycle Timings .............................

Figure 22. Data# Polling Timings (During Embedded Algorithms) .......

Figure 23. Toggle Bit Timings (During Embedded Algorithms) ............

Figure 24. DQ2 vs. DQ6 .......................................................................

SecSi

(Secured Silicon) Sector

Flash Memory Region ..................................................................20

Figure 3. SecSi Sector Protect Verify.................................................... 21

Hardware Data Protection ............................................................21

Temporary Sector Unprotect ........................................................ 45

Figure 25. Temporary Sector Unprotect Timing Diagram..................... 45

Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram 46

Common Flash Memory Interface (CFI) . . . . . . . 21

Table 9. CFI Query Identification String ................................................

Table 10. System Interface String.........................................................

Table 11. Device Geometry Definition ..................................................

Table 12. Primary Vendor-Specific Extended Query ............................

Alternate CE# Controlled Erase and Program Operations ........... 47

Figure 27. Alternate CE# Controlled Write (Erase/Program)

Operation Timings ................................................................................ 48

Reading Array Data ......................................................................24

Reset Command ..........................................................................24

Autoselect Command Sequence ..................................................24

Enter SecSi

Sector/Exit SecSi Sector

Command Sequence ...................................................................25

Byte/Word Program Command Sequence ................................... 25

Figure 4. Program Operation ................................................................ 26

Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 49

TSOP And SO Pin Capacitance . . . . . . . . . . . . . . 49

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm . 50

FBD048—Fine-Pitch Ball Grid Array, 6 x 12 mm ......................... 51

TS 048—Thin Small Outline Package .......................................... 52

Chip Erase Command Sequence .................................................26

Am29DL320G

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