Micro Networks
An Integrated Circuit Systems Company
M2004-01
Preliminary Specifications
M2004-01
Frequency Synthesizer
DESCRIPTION
The M2004-01 integrates a high performance Phase
Locked Loop (PLL) with a Voltage Controlled SAW
Oscillator (VCSO) to provide a low jitter Frequency
Translator in a 9mm x 9mm surface mount package.
The internal high “Q” SAW filter provides low jitter
signal performance and determines the maximum
output frequency of the VCSO. A programmable
output divider can divide the VCSO frequency to
achieve an output as low as 38.88MHz.
FEATURES
Output Clock Frequency up to 700MHz
Differential LVPECL Outputs
Internal Low-jitter SAW-based Oscillator
Intrinsic Jitter <1ps rms (12kHz - 20MHz)
Jitter Attenuation of Input Reference Clock
Dual Input MUX
Parallel Programming
Tunable Loop Filter Response
Differential LVPECL Outputs
3.3V Operation
Small 9mm x 9mm SMT Package
The input to the Frequency Translator is provided by
selecting between one of two output reference
clocks. The output frequency is an integer multiple
of the input reference frequency.
Parallel and serial control of the output and
feedback dividers is provided via the configuration
logic. An external loop filter sets the PLL bandwidth
which can be optimized to provide jitter attenuation
of the input reference clock.
The M2004-01 is available at SONET/SDH and
10GbE frequencies up to 700MHz.
APPLICATIONS
ABSOLUTE MAX RATINGS
Inputs, V
I
:
................................................. -0.5 to V
CC
+0.5V
Output, V
O
: ................................................. -0.5 to V
CC
+0.5V
Supply Voltage, V
DD
: ......................................................... 4.6 V
Storage Temperature, T
STO
: ............................ -45°C to +100°C
Stresses beyond those listed under Absolute Maximum Ratings may cause
permanent damage to the device. These ratings are stress specifications
only. Functional operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
SONET / SDH / 10GbE System
Synchronization
Add / Drop Muxes, Access and Edge
Switches
Line Card System Clock Cleaner /
Translator
Optical Module Clock Cleaner / Translator
ISO 9001
Registered
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
1
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company
FUNCTIONAL BLOCK DIAGRAM
M2004-01
Preliminary Specifications
The internal PLL will adjust the VCSO output
frequency to be M times the selected input
reference clock frequency. Note that the product of
M x input frequency must be such that it falls within
the “lock” range of the VCSO. The N output divider
can be programmed to divide the VCSO output
frequency by 1, 2, 4, or 8 and provide a 50% output
duty cycle.
RLOOP CLOOP
RPOST
CPOST
CPOST
RLOOP CLOOP
RPOST
nOP_OUT nVC
VC
SAW Delay Line
The relationship between the VCSO frequency, the
input REF_CLK , and the M divider is defined as
follows:
F VCSO = F REF_CLK x M
When the N output divider is included, the
complete relationship for the output frequency is
defined as:
FOUT= F VCSO = F REF_CLK x M
N
N
The M value and the required logic states of M0
through M5 are shown in Table 5B, Programmable
VCSO Frequency Function Table. (i.e. For an output
frequency of 622.0800MHz and an input frequency
of 19.44MHz the M value would be 32 and the N
value would be 1.
Similarly, for an output frequency of 311.04MHz
and an input frequency of 19.44 MHz the M value
would be 32 and the N value would be 2.) Serial
operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by
sampling the S_DATA bits with the rising edge of
S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider
when S_LOAD transitions from LOW-to-HIGH. The
M divider and N output divide values are latched on
the HIGH-to-LOW transition of S_LOAD. If S_LOAD
is held HIGH, data at the S_DATA input is passed
directly to the M divider and N output divider on
each rising edge of S_CLOCK.
External
Loop Filter
Components
M2004-01
OP_IN
nOP_IN OP_OUT
REF_CLK1
REF_CLK0
REF_SEL
Phase
MUX
Detector
RIN
1
0
RIN
Loop Filter
Amplifier
M Divider
M = 3-1023
Phase
Shifter
VCSO
S_DATA
S_CLK
S_LOAD
nP_LOAD
N Divider
N = 1,2,4,8
Serial / Parallel
Configuration Register
FOUT
nFOUT
6
M5:0
2
N1:0
MR
The M2004-01 supports both parallel and serial
operating modes for programming the M divider
and N output divider. Figure 1 shows the timing
diagram for each mode. In the parallel mode the
nP_LOAD input is initially LOW. The data on inputs
M0 through M5 and N0 and N1 is passed directly to
the M divider. On the LOW-to-HIGH transition of
the nP_LOAD input, the data is latched and the M
divider remains loaded until the next LOW transition
on nP_LOAD or until a serial event occurs. As a
result, the M and N bits can be hardwired to set the
M divider and N output divider to a specific default
state that will automatically occur during power-up.
FIGURE 1
S_DATA
Low Low Null
N1
N0 Null Null Null M5
M4
M3
M2
M1
M0
S_CLK
S_LOAD
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
2
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company
FUNCTIONAL DESCRIPTION
LOOP FILTER
FIGURE 2
Rloop
OP_IN
Cloop
M2004-01
Preliminary Specifications
The M2004-01 requires the use of an external loop
filter via the provided filter pins. Due to the
differential design, the implementation requires two
identical RC filters as shown in Figure 2.
Rpost
nVc
Cpost
nOP_OUT
OP_OUT
Cpost
nOP_IN
Rloop
Cloop
Rpost
Vc
TABLE 1. RECOMMENDED LOOP FILTER VALUES
REF_CLK
Frequency
19.44MHz
VCSO
Frequency
622.0800MHz
M
N
FOUT
Rloop
Cloop
Rpost
Cpost
32
1
622.0800MHz
5kΩ
1MF
50kΩ
100pf
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
3
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company
PIN DESCRIPTIONS
TABLE 2
Pin Number
1, 2, 3
Name
M2004-01
Preliminary Specifications
GND
OP_IN, nOP_IN
nOP_OUT, OP_OUT
nVC, VC
GND
VDD
N0, N1
FOUT, nFOUT
MR
I/O
GND
Configuration
Description
Power Supply Ground
4, 9
5, 8
6, 7
10, 14, 26
11, 19, 33
12, 13
15, 16
17
Analog I/O
Analog I/O
Input
GND
Power
Input
Output
Input
Pull - down
Unterminated
Pull - down
VCSO
Used for external loop filter. See Figure 2.
Used for external loop filter. See Figure 2
Differential Control Voltage Input Pair
Power Supply Ground
Positive Supply Pins
Determines the output divider value as defined in
table 3C. LVCMOS / LVTTL interface levels.
Differential output, 3.3V LVPECL levels.
Logic HIGH resets the reference frequency and N
output dividers. Logic LOW enables the outputs.
LVCMOS / LVTTL interface levels.
18
S_CLOCK
Input
Pull - down
Clocks in serial data present at S_DATA input
into the shift register on the rising edge of
S_CLOCK.
20
21
22
S_DATA
S_LOAD
nP_LOAD
Input
Input
Input
Pull - down
Pull - down
Pull - down
Shift register serial input. Data is sampled on the
rising edge of S_CLOCK.
Controls transition of data from shift register into
the dividers. LVCMOS / LVTTL interface levels
Parallel load input. Determines when data
present at M5:M0 is loaded into Mdivider, and
when data present at N1:N0 sets the N output
divider value. LVCMOS / LVTTL interface levels.
23
24
25
REF_ CLK 1
REF_ CLK 0
REF_SEL
Input
Input
Input
Pull - down
Pull - down
Pull - down
Input reference clock. LVCMOS / LVTTL interface
levels.
Input reference clock. LVCMOS / LVTTL interface
levels.
Selects between the different reference clock
inputs as the PLL reference source. See table 3D.
LVCMOS / LVTTL interface levels.
27, 28, 29, 30, 31
M0, M1, M2, M3, M4 Input
Pull - down
M divider inputs. Data is latched on LOW-to-HIGH
transition of nP_LOAD input. LVCMOS/ LVTTL
interface levels.
32
34, 35, 36
M5
DNC
Input
Pull - down
Do not connect. Internal test pins must be left
floating.
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
4
fax: 508-852-8456
www.micronetworks.com
Micro Networks
An Integrated Circuit Systems Company
PIN CHARACTERISTICS
TABLE 4
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Min
Typical
M2004-01
Preliminary Specifications
Max
4
Units
pF
R
PULLUP
R
PULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
51
51
kΩ
kΩ
PARALLEL & SERIAL MODES FUNCTION
TABLE 5A
MR
H
nP Load
X
M
X
Inputs
N
X
S Load S Clock S Data
X
X
X
Conditions
Reset, Forces outputs LOW.
L
L
L
↑
Data
Data
Data
Data
X
L
X
X
X
X
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
Data is latched into input registers and remains
loaded until next LOW transition or until a serial event
occurs.
L
L
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
L
↑
↑
Data
Data
Data
X
Data
Serial input mode. Shift register is loaded with data
on S_DATA on each rising edge of S_CLOCK
Contents of the shift register are passed to the M
divider and N output divider.
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
L
L
X
↑
↓
L
H
Note: L = Low; H = High; X = Don’t care;
↑
= Rising Edge Transition;
↓
= Falling Edge Transition
PROGRAMMABLE VCSO FREQUENCY FUNCTION
TABLE 5B
VCSO Frequency
(MHz)
325
M Divide
13
32
M5
0
0
0
0
•
•
0
0
0
16
M4
0
0
0
1
•
•
1
1
1
8
M3
1
1
1
0
•
•
1
1
1
4
M2
1
1
1
0
•
•
0
0
0
2
M1
0
1
1
0
•
•
0
0
1
1
M0
1
0
1
0
•
•
0
1
0
350
375
400
•
•
600
625
650
14
15
16
•
•
24
25
26
NOTE 1: These M divide values and the resulting frequencies correspond to a reference frequency of 25MHz.
Micro Networks
324 Clark Street
Worcester, MA 01606
tel: 508-852-5400
5
fax: 508-852-8456
www.micronetworks.com
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