If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
−0.3V to +4V
CMOS/TTL Output Voltage
−0.3V to (V
CC
+ 0.3V)
LVDS Receiver Input Voltage
−0.3V to (V
CC
+ 0.3V)
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
Lead Temperature
(Soldering, 4 sec)
+260˚C
Solder Reflow Temperature
(20 sec for FBGA)
+220˚C
Maximum Package Power Dissipation Capacity
@
25˚C
MTD56 (TSSOP) Package:
DS90CR286AMTD
1.61 W
MTD48 (TSSOP) Package:
DS90CR216AMTD
1.89 W
SLC64A Package:
DS90CR286ASLC
Package Derating:
DS90CR286AMTD
DS90CR216AMTD
DS90CR286ASLC
ESD Rating
(HBM, 1.5 kΩ, 100 pF)
(EIAJ, 0Ω, 200 pF)
2.0W
12.4 mW/˚C above +25˚C
15 mW/˚C above +25˚C
10.2 mW/˚C above +25˚C
>
7 kV
>
700V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Operating Free Air
Temperature (T
A
)
Receiver Input Range
Supply Noise Voltage (V
CC
)
Min
3.0
−40
0
Nom
3.3
+25
Max
3.6
+85
2.4
100
Units
V
˚C
V
mV
PP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
V
IH
V
IL
V
CL
I
IN
Parameter
High Level Input Voltage
Low Level Input Voltage
Input Clamp Voltage
Input Current
I
CL
= −18 mA
V
V
CMOS/TTL DC SPECIFICATIONS
V
OH
V
OL
I
OS
V
TH
V
TL
I
IN
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
Differential Input High Threshold
Differential Input Low Threshold
Input Current
V
V
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current Worst Case
C
L
= 8 pF, Worst
Case Pattern,
DS90CR286A
(Figures
1, 2 ),
T
A
=−10˚C to
+70˚C
C
L
= 8 pF, Worst
Case Pattern,
DS90CR286A
(Figures
1, 2 ),
T
A
=−40˚C to
+85˚C
C
L
= 8 pF, Worst
Case Pattern,
DS90CR216A
(Figures
1, 2 ),
T
A
=−10˚C to
+70˚C
f = 33 MHz
f = 37.5 MHz
f = 66 MHz
f = 40 MHz
49
53
81
53
65
70
105
70
mA
mA
mA
mA
IN
IN
IN
IN
Conditions
Min
2.0
GND
Typ
Max
V
CC
0.8
Units
V
V
V
µA
µA
V
CMOS/TTL DC SPECIFICATIONS (For PowerDown Pin)
−0.79
+1.8
−10
2.7
0
3.3
0.06
−60
−1.5
+10
= 0.4V, 2.5V or V
CC
= GND
I
OH
= −0.4 mA
I
OL
= 2 mA
V
OUT
= 0V
V
= +1.2V
0.3
−120
+100
V
mA
mV
mV
µA
µA
LVDS RECEIVER DC SPECIFICATIONS
CM
−100
= +2.4V, V
CC
= 3.6V
= 0V, V
CC
= 3.6V
±
10
±
10
ICCRW
Receiver Supply Current Worst Case
f = 66 MHz
81
105
mA
ICCRW
Receiver Supply Current Worst Case
f = 33 MHz
f = 37.5 MHz
f = 66 MHz
49
53
78
55
60
90
mA
mA
mA
www.national.com
2
DS90CR286A/DS90CR216A
Electrical Characteristics
Symbol
ICCRW
Parameter
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Conditions
C
L
= 8 pF, Worst
Case Pattern,
DS90CR216A
(Figures
1, 2 ),
T
A
=−40˚C to
+85˚C
Power Down = Low
Receiver Outputs Stay Low during
Power Down Mode
Note 1:
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2:
Typical values are given for V
CC
= 3.3V and T
A
= +25C.
Note 3:
Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V
OD
and
∆V
OD
).
Min
f = 40 MHz
Typ
53
Max
60
Units
mA
RECEIVER SUPPLY CURRENT
Receiver Supply Current Worst Case
f = 66 MHz
78
90
mA
ICCRZ
Receiver Supply Current
Power Down
10
55
µA
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSPos0
RSPos1
RSPos2
RSPos3
RSPos4
RSPos5
RSPos6
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time
(Figure 2 )
CMOS/TTL High-to-Low Transition Time
(Figure 2 )
Receiver Input Strobe Position for Bit 0
(Figure 9,
Figure 10)
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
Receiver Input Strobe Position for Bit 0
(Figure 9,
Figure 10)
Receiver Input Strobe Position for Bit 1
Receiver Input Strobe Position for Bit 2
Receiver Input Strobe Position for Bit 3
Receiver Input Strobe Position for Bit 4
Receiver Input Strobe Position for Bit 5
Receiver Input Strobe Position for Bit 6
RxIN Skew Margin (Note 4)
(Figure 11 )
RxCLK OUT Period
(Figure 3)
RxCLK OUT High Time
(Figure 3 )
RxCLK OUT Low Time
(Figure 3)
RxOUT Setup to RxCLK OUT
(Figure 3 )
RxOUT Hold to RxCLK OUT
(Figure 3 )
RxCLK OUT High Time
(Figure 3 )
RxCLK OUT Low Time
(Figure 3)
RxOUT Setup to RxCLK OUT
(Figure 3 )
RxOUT Hold to RxCLK OUT
(Figure 3 )
RxCLK IN to RxCLK OUT Delay 25˚C, V
CC
= 3.3V (Note 5)(Figure
4 )
Receiver Phase Lock Loop Set
(Figure 5 )
Receiver Power Down Delay
(Figure 8 )
3
Min
Typ
2
1.8
Max
5
5
2.15
5.8
9.15
12.6
16.3
19.9
23.6
1.4
3.6
5.8
8.0
10.2
12.4
14.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
f = 40 MHz
1.0
4.5
8.1
11.6
15.1
18.8
22.5
1.4
5.0
8.5
11.9
15.6
19.2
22.9
1.1
3.3
5.5
7.7
9.9
12.1
14.3
f = 66 MHz
0.7
2.9
5.1
7.3
9.5
11.7
13.9
f = 40 MHz
f = 66 MHz
f = 40 MHz
490
400
15
10.0
10.0
6.5
6.0
T
12.2
11.0
11.6
11.6
7.6
6.3
7.3
6.3
5.0
7.5
10
1
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
f = 66 MHz
5.0
5.0
4.5
4.0
3.5
www.national.com
DS90CR286A/DS90CR216A
Receiver Switching Characteristics
(Continued)
Note 4:
Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol inter-
ference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
Note 5:
Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
for the 215/285 transmitter and 216A/286A receiver is: (T + TCCD) + (2
*
T + RCCD), where T = Clock period.
AC Timing Diagrams
DS100873-2
FIGURE 1. “Worst Case” Test Pattern
DS100873-4
FIGURE 2. DS90CR286A/DS90CR216A (Receiver) CMOS/TTL Output Load and Transition Times
DS100873-5
FIGURE 3. DS90CR286A/DS90CR216A (Receiver) Setup/Hold and High/Low Times
DS100873-6
FIGURE 4. DS90CR286A/DS90CR216A (Receiver) Clock In to Clock Out Delay
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