DS1086LPMB1 Peripheral Module
General Description
The DS1086LPMB1 peripheral module provides the
necessary hardware to interface the DS1086L 3.3V
spread-spectrum EconOscillatorK to any system that
utilizes PmodK-compatible expansion ports configurable
for I
2
C communication. The DS1086L is a program-
mable clock generator that produces a spread-spectrum
(dithered) square-wave output of frequencies from
130kHz to 66.6MHz. The selectable dithered output
reduces radiated-emission peaks by dithering the
frequency 0.5%, 1%, 2%, 4%, or 8% below the
programmed frequency. The DS1086L has a power-down
mode and an output-enable control for power-sensitive
applications.
Refer to the DS1086L IC data sheet for detailed informa-
tion regarding operation of the IC.
Features
S
User-Programmable 130kHz to 66.6MHz Square
Wave
S
No External Timing Components Required
S
6-Pin Pmod-Compatible Connector (I
2
C)
S
Example Software Written in C for Portability
S
Secondary Header Allows Daisy-Chaining of
Additional Modules on the I
2
C Bus
S
Output Header Provides Access to Control Signals
for External Circuitry
S
RoHS Compliant
S
Proven PCB Layout
S
Fully Assembled and Tested
Ordering Information
appears at end of data sheet.
DS1086LPMB1 Peripheral Module
EconOscillator is a trademark of Maxim Integrated Products,
Inc.
Pmod is a trademark of Digilent Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-6318; Rev 0; 5/12
DS1086LPMB1 Peripheral Module
Component List
DESIGNATION
C1
QTY
1
DESCRIPTION
0.01FF
Q10%,
16V X7R ceramic
capacitor (0603)
Murata GRM188R71C103KA01D
0.1FF
Q10%,
16V X7R ceramic
capacitor (0603)
Murata GRM188R71C104KA01D
12-pin (2 x 6) right-angle male
header
8-pin (2 x 4) straight male header
DESIGNATION
J3
R1, R2, R8,
R9, R10
R3, R4, R5
R6, R7
U1
—
QTY
1
5
3
2
1
1
DESCRIPTION
5-pin straight male header
4.7kI
Q5%
resistors (0603)
1kI
Q5%
resistors (0603)
150kI
Q5%
resistors (0603)
3.3V spread-spectrum
EconOscillator (8
FSOP)
Maxim DS1086LU+
PCB: EPCB1086L
C2
1
J1
J2
1
1
Component Supplier
SUPPLIER
Murata Electronics North America, Inc.
PHONE
770-436-1300
WEBSITE
www.murata-northamerica.com
Note:
Indicate that you are using the DS1086LPMB1 when contacting this component supplier.
Detailed Description
The DS1086LPMB1 peripheral module can interface to
the host in one of two ways. It can plug directly into a
Pmod-compatible port (configured for I
2
C) through con-
nector J1, or in this case, other I
2
C boards can attach to
the same I
2
C bus through connector J2.
Table 1. Connector J1 (I
2
C Communication)
PIN
SIGNAL
DESCRIPTION
Power-down. When the pin is high, the
output buffer is enabled. When the pin
is low, the master oscillator is disabled
(power-down mode).
Dither enable. When the pin is high, the
dither is enabled. When the pin is low,
the dither is disabled.
I
2
C serial clock
I
2
C serial data
Ground
Power supply
Output enable. When the pin is high,
the output buffer is enabled. When the
pin is low, the output is disabled but the
master oscillator is still on.
Not connected
I
2
C serial clock
I
2
C serial data
Ground
Power supply
I2C Interface
1
PDN
Alternatively, the peripheral module can connect to other
I
2
C-based Pmod modules using a 4-conductor ribbon
cable connecting to the J2 connector. In this situation,
pins 1-4 and 5-8 of J2 provide two connections to the I
2
C
bus, allowing the module to be inserted into an I
2
C bus
daisy-chain.
I2C Interface
(Daisy-Chaining Modules)
2
3
4
5
6
SPRD
SCL
SDA
GND
VCC
Connector J1 provides connection of the module to the
Pmod host. The pin assignments and functions adhere
to the Pmod standard recommended by Digilent. See
Table 1.
The J2 connector allows the module to be connected
through a daisy-chain from another I
2
C module and/or
provide I
2
C and power connections to other I
2
C modules
on the same bus. See Table 2.
7
OE
8
9
10
11
12
N.C.
SCL
SDA
GND
VCC
Maxim Integrated
2
DS1086LPMB1 Peripheral Module
External Control Signals
Studio, and SDK projects. In addition, a synthesized bit
stream, ready for FPGA download, is provided for the
demonstration application.
The software project (for the SDK) contains several
source files intended to accelerate customer evalu-
ation and design. These include a base application
(maximModules.c) that demonstrates module function-
ality and uses an API interface (maximDeviceSpecific
Utilities.c) to set and access Maxim device functions
within a specific module.
The source code is written in standard ANSI C format, and
all API documentation including theory/operation, register
description, and function prototypes are documented in
the API interface file (maximDeviceSpecificUtilities.h & .c).
The complete software kit is available for download
www.maximintegrated.com.
Quick start instructions are
also available as a separate document.
The IC implements pins to control output enable (OE),
power-down (PDN), and dither enable (SPRD). These
pins can be controlled either by the host (through the
Pmod connector) or by external circuitry through the
5-pin output connector. In cases where one or more
of these signals is driven from an external source, 1kI
resistors R3, R4, and R5 limit the current to/from the
host. However, this also increases the apparent load to
the external driving source. If the external source is inca-
pable of driving this load (1kI
||
4.7kI), the signal(s) from
the host should either be put into three-state (open) or
resistors R3, R4, and/or R5 should be removed.
The J3 connector provides the output signal as well as
external inputs to the control signals. Note that the con-
trol lines from the host (SPRD,
PND,
OE) must either be
three-stated or the external control signals must be able
to drive the additional load. See Table 3.
Example software and drivers are available that execute
directly without modification on several FPGA devel-
opment boards that support an integrated or synthe-
sized microprocessor. These boards include the Digilent
Nexys 3, Avnet LX9, and Avnet ZEDBoard, although
other platforms can be added over time. Maxim provides
complete Xilinx ISE projects containing HDL, Platform
Software and FPGA Code
Table 3. Connector J3 (External Interface)
PIN
1
2
SIGNAL
OUT
GND
SPRD
DESCRIPTION
Oscillator output. The output frequency is
set by the OFFSET, DAC, and prescaler
registers.
Ground
Dither enable. When the pin is high, the
dither is enabled. When the pin is low,
the dither is disabled.
Power-down. When the pin is high, the
output buffer is enabled. When the pin
is low, the master oscillator is disabled
(power-down mode).
Output enable. When the pin is high,
the output buffer is enabled. When the
pin is low, the output is disabled but the
master oscillator is still on.
Table 2. Connector J2 (I
2
C Expansion)
PIN
1
2
3
4
5
6
7
8
SIGNAL
SCL
SDA
GND
VCC
SCL
SDA
GND
VCC
DESCRIPTION
I
2
C serial clock
I
2
C serial data
Ground
Power supply
I
2
C serial clock
I
2
C serial data
Ground
Power supply
3
4
PDN
5
OE
Maxim Integrated
3
DS1086LPMB1 Peripheral Module
VCC VCC
R1
4.7k
PDN
SPRD
R2
4.7k
R3
R5
R6
R7
1k
1k
150
150
J1
SCL
SDA
GND
VCC
1
2
3
4
5
6
7
8
9
10
11
12
R4
1k
OE
SCL
SDA
J2
1
2
3
4
5
6
7
8
GND
VCC
C1
VCC
C2
DS1086L
VCC
0.01uF
GND
0.1uF
VCC
VCC
R8
4.7k
VCC
R9
4.7k
VCC
R10
4.7k
7
8
5
6
2
U1
SDA
SCL
OE
PDN
SPRD
GND
3
OUT
1
OUT
J3
GND
1
2
3
4
5
4
GND
SPRD
PDN
OE
Figure 1. DS1086LPMB11 Peripheral Module Schematic
Maxim Integrated
4
DS1086LPMB1 Peripheral Module
Figure 2. DS1086LPMB11 Peripheral Module Component Placement Guide—Component Side
Figure 3. DS1086LPMB11 Peripheral Module PCB Layout—Component Side
Figure 4. DS1086LPMB11 Peripheral Module PCB Layout—Inner Layer 1 (Ground)
Maxim Integrated
5
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