FS8160 1.1 GHz/1.1 GHz Dual Phase-locked Loop IC
HiMARK Technology, Inc. reserves the right to change the product described in this datasheet. All information con-
tained in this datasheet is subject to change without prior notice. HiMARK Technology, Inc. assumes no responsibility
for the use of any circuits shown in this datasheet.
Description
The FS8160 is a serial data input, fully programmable dual phase-locked loop IC for use
in the local oscillator subsystem of radio transceivers. When combined with external
VCOs, the FS8160 becomes the core of a very low power dual frequency synthesizer well-
suited for mobile communication applications.
The FS8160 is pin-compatible with
National Semiconductor’s LMX1602 IC.
Features
Supply voltage operating range: 2.7 to 3.6 V
Maximum input frequency: 1.1 GHz/1.1 GHz (main/auxiliary)
Low current consumption (I
DD,total
typically 5 mA at V
DD,main
= V
DD,aux
= 3.0 V and < 1
µA
in power down mode)
16-bit programmable input (both main and auxiliary) frequency dividers (including a
÷ 16/17
prescaler) with divide ratio range from 240 to 65535
12-bit programmable reference (both main and auxiliary) frequency dividers with
divide ratio range from 2 to 4095
Programmable charge pump output
Digital-filtered lock detect output
16 pin, plastic TSSOP (0.65 mm pitch)
Package and Pin Assignment
16 pin, plastic TSSOP (dimensions in mm)
FOLD
XIN
XOUT
VSSA
FINA
VDDA
DOA
ENA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK
DATA
LE
VSSM
FINM
VDDM
DOM
ENM
HiMARK
FS8160
Page 1
April 2003
FS8160
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
FOLD
XIN
XOUT
VSSA
FINA
VDDA
DOA
ENA
ENM
DOM
VDDM
FINM
VSSM
LE
DATA
CLK
I/O
O
I
O
—
I
—
O
I
I
O
—
I
—
I
I
I
Description
Multiplexed CMOS level output (see Programming Description section)
Reference crystal oscillator or external clock input with internally biased amplifier
Reference crystal oscillator output used with external resonator
Ground (aux PLL)
VCO frequency input with internally biased input amplifier (aux PLL)
Nominal 3.0 V supply voltage (aux PLL)
Single-ended charge pump output (aux PLL)
Enable control input; normal operation when high, power-down mode when low (aux PLL)
Enable control input; normal operation when high, power-down mode when low (main PLL)
Single-ended charge pump output (main PLL)
Nominal 3.0 V supply voltage (main PLL)
VCO frequency input with internally biased input amplifier (main PLL)
Ground (main PLL)
Latch enable input
Serial data input
Shift register clock input
Functional Block Diagram
FINM
XIN
XOUT
DATA
CLK
LE
ENM
ENA
MAIN
PRESCALER
N-COUNTER
PFD
R-COUNTER
MAIN LATCH
LOCK
DETECTOR
FOLD
MUX
LOCK
DETECTOR
CHARGE
PUMP
DOM
OSC
CONTROL
LOGIC
SHIFT REGISTER
FOLD
AUX LATCH
R-COUNTER
FINA
AUX
PRESCALER
PFD
N-COUNTER
CHARGE
PUMP
DOA
Page 2
April 2003
FS8160
Absolute Maximum Ratings
V
SS
= 0 V
Parameter
Supply voltage
Symbol
V
DD,main
V
DD,aux
V
FIN,main
V
FIN,aux
T
OPR
T
STG
T
SLD
t
SLD
Rating
V
SS
– 0.3 to V
SS
+ 6.5
V
SS
– 0.3 to V
SS
+ 6.5
V
SS
– 0.3 to V
DD,main
+ 0.3
V
SS
– 0.3 to V
DD,aux
+ 0.3
–40 to 85
–40 to 125
255
10
Unit
V
V
V
V
°C
°C
°C
s
Input voltage range
Operating temperature range
Storage temperature range
Soldering temperature range
Soldering time range
Recommended Operating Conditions
V
SS
= 0 V
Value
Parameter
Symbol
min.
V
DD,main
Supply voltage range
V
DD,aux
Operating temperature
T
A
V
DD,main
–40
25
V
DD,main
85
V
°C
2.7
typ.
max.
3.6
V
Unit
Page 3
April 2003
FS8160
Electrical Characteristics
(V
DD,main
= V
DD,aux
= V
DD
= 3.0 V, T
A
= 25 °C unless otherwise noted)
Value
Parameter
Symbol
Condition
min.
GENERAL
Current consumption
Standby current consumption
FIN operating frequency range
I
DD,total
I
DD,standby
f
FIN
1.1 GHz + 1.1 GHz
1.1 GHz only
ENM = ENA = low
Main
Auxiliary
Logic mode
Crystal mode
Main
Auxiliary
100
100
1
1
–15
–15
0.5
5.0
2.5
1
1100
1100
40
20
0
0
V
DD,aux
Unit
typ.
max.
mA
mA
µA
MHz
MHz
MHz
MHz
dBm
dBm
V
pk-pk
XIN operating frequency range
f
XIN
FIN input sensitivity
XIN input sensitivity
DIGITAL INTERFACE
Logic LOW input voltage
Logic HIGH input voltage
Logic LOW input current
Logic HIGH input current
XIN logic LOW input current
XIN logic HIGH input current
P
FIN
V
XIN
V
IL
V
IH
I
IL
I
IH
I
IL,XIN
I
IH,XIN
V
IL
= 0 V, V
DD
= 3.6 V
V
IH
= V
DD
= 3.6 V
V
IL
= 0 V, V
DD
= 3.6 V
V
IH
= V
DD
= 3.6 V
Logic mode, V
XOUT
=
V
DD
/2, V
DD
= 3.6 V
Crystal mode, V
XOUT
=
V
DD
/2, V
DD
= 2.7 V
I
OL
= 500
µA
I
OH
= –500
µA
V
DD
–
0.4
|300|
0.8 ×
V
DD
–1
–1
–100
0.2 ×
V
DD
V
V
1
1
µA
µA
µA
100
|200|
µA
µA
µA
XOUT output current magnitude
I
XOUT
Logic LOW output voltage
Logic HIGH output voltage
SERIAL PROGRAMMING TIMING
DATA to CLK setup time
DATA to CLK hold time
V
OL
V
OH
0.4
V
V
t
SU1
t
H1
50
10
nS
nS
Page 4
April 2003
FS8160
Electrical Characteristics (continued)
(V
DD,main
= V
DD,aux
= V
DD
= 3.0 V, T
A
= 25 °C unless otherwise noted)
Value
Parameter
Symbol
Condition
min.
CLK to LE setup time
CLK pulse width logic HIGH
CLK pulse width logic LOW
LE pulse width
CHARGE PUMP
High gain mode,
V
DOM
,V
DOA
= V
DD
/2
Low gain mode,
V
DOM
,V
DOA
= V
DD
/2
High gain mode,
V
DOM
,V
DOA
= V
DD
/2
Low gain mode,
V
DOM
,V
DOA
= V
DD
/2
0.5 V
≤
V
DOM
,V
DOA
≤
V
DD
–
0.5 V
Unit
typ.
max.
nS
nS
nS
nS
t
SU2
t
PWH
t
PWL
t
PW
50
50
50
50
–1600
µA
µA
µA
µA
nA
I
DO,source
Charge pump output current
I
DO,sink
–160
+1600
+160
1
Charge pump high-Z state current
I
DO,high-Z
Page 5
April 2003
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