SiM3C1xx
High-Performance, Low-Power, 32-Bit Precision32™
MCU Family with up to 256 kB of Flash
32-bit ARM® Cortex™-M3 CPU
-
80 MHz maximum frequency
-
Single-cycle multiplication, hardware division support
-
Nested vectored interrupt control (NVIC) with 16 priority levels
Memory
-
32–256 kB Flash, in-system programmable
-
8–32 kB SRAM (including 4 kB retention SRAM)
-
16-channel DMA controller
-
External bus interface supports up to 16 MB of external mem-
ory and a parallel LCD interface with QVGA resolution
Analog Peripherals
-
2 x 12-Bit Analog-to-Digital Converters: Up to 250 ksps 12-bit
-
mode or 1 Msps 10-bit mode, internal or external reference
2 x 10-Bit Current-mode Digital-to-Analog Converters, four-
word buffer enables 12-bit operation
2 x Low-current comparators
-
-
16-Channel Capacitance-to-Digital: Fast, <1 µA wake-on-touch
-
2 x Current-to-Voltage Converter, up to 6 mA input range
Digital and Communication Peripherals
-
2 x USARTs and 2 x UARTs with IrDA and ISO7816 SmartCard
-
3 x SPIs, 2 x I2C, I
2
S (receive and transmit), 16/32-bit CRC
-
128/192/256-bit Hardware AES Encryption
Timers/Counters
-
2 x 32-bit or 4 x 16-bit timers with capture/compare
-
2 x 16-bit, 2-channel counters with capture/compare/PWM
-
16-bit, 6-channel counter with capture/compare/PWM and
-
-
32-bit real time clock (RTC) with multiple alarms
-
Watchdog timer
dead-time controller with differential outputs
16-bit low power timer/pulse counter operational in sleep
Power Management
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Low drop-out (LDO) regulator
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Power-on reset circuit and brownout detectors
-
5-to-3.3 V 150 mA regulator supports up to 5 V input supply
-
Adjustable external regulator supports up to 3.6 V, 1000 mA
-
Multiple power modes supported for low power optimization
Low Power Features
-
85 nA current mode with voltage supply monitor enabled
-
Low-current RTC: 350 nA internal LFO, 620 nA external crystal
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12 µs wakeup (lowest power mode); 1.5 µs analog setting time
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275 µA/MHz active current
-
Clocks can be gated off from unused peripherals to save power
-
Flexible clock divider: Reduce operational frequency up to 128x
Clock Sources
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Internal oscillator with PLL: 23–80 MHz, reduced EMI mode
-
Low power internal oscillator: 20 MHz and 2.5 MHz modes
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Low frequency internal oscillator: 16.4 kHz
-
External oscillators: Crystal, RC, C, CMOS and RTC Crystal
Temperature Range: –40 to +85 °C
Package Options
-
QFN options: 40-pin (6 x 6 mm), 64-pin (9 x 9 mm)
-
TQFP options: 64-pin (10 x 10 mm), 80-pin (12 x 12 mm)
-
LGA option: 92-pin (7 x 7 mm)
Up to 65 Flexible I/O
-
Up to 59 contiguous GPIO with two priority crossbars providing
-
flexibility in pin assignments; 12 x 5 V tolerant GPIO
Up to 6 programmable high drive capable (5–300 mA, 1.8–6 V)
I/O can drive LEDs, power MOSFETs, buzzers, etc.
On-Chip Debugging
-
Serial wire debug (SWD) or JTAG (no boundary scan), serial
-
wire viewer (SWV)
Cortex-M3 embedded trace macrocell (ETM)
Supply Voltage
-
2.7 to 5.5 V (regulator enabled)
-
1.8 to 3.6 V (regulator disabled)
Power
5 V In, 3.3 V Out LDO
1.8 V Internal LDO
(Internal Logic and Memory Power)
External 1A Regulator
Power Management Unit
Supply Monitor
Core / Memory / Support
ARM Cortex M3 (80 MHz)
32/64/128/256 kB Flash
8/16/32 kB SRAM w/ 4kB Retention
16-Channel DMA Controller
Watchdog
Serial Wire / JTAG / ETM
Analog Peripherals
2 x SAR ADC
(12-bit 250 ksps / 10-bit 1 Msps)
Voltage Reference
2 x Current-Source DAC
2 x Low Current Comparators
2 x Current-to-Voltage Converter
16-Channel Capacitive Sense
65 Multi-Function I/O Pins (12 x 5 V tol, 6 x High-Drive)
Flexible Pin Muxing
Two Priority Crossbar
Encoders
Clocking / Oscillators
80 MHz PLL
Real-Time Clock w/ Dedicated Crystal
16 kHz Low Frequency Oscillator
20 MHz Low Power Oscillator
External Oscillator Drive
Clock Selection
and Gating
I2S TX/RX
Digital Peripherals
2 x I2C
3 x SPI
AES
CRC
2 x 32-bit Timers (4 x 16-bit)
2 x UART, 2 x USART w/ IrDA/SmartCard
6-Channel Enhanced PWM
2 x 2-Channel Standard PWM
Low-Power Timer
External Parallel I/F
Rev.1.0 11/12
Copyright © 2012 by Silicon Laboratories
SiM3C1xx
SiM3C1xx
Ta ble of Contents
1. Related Documents and Conventions ...............................................................................4
1.1. Related Documents........................................................................................................4
1.1.1. SiM3U1xx/SiM3C1xx Reference Manual...............................................................4
1.1.2. Hardware Access Layer (HAL) API Description ....................................................4
1.1.3. ARM Cortex-M3 Reference Manual.......................................................................4
1.2. Conventions ...................................................................................................................4
2. Typical Connection Diagrams ............................................................................................5
2.1. Power .............................................................................................................................5
3. Electrical Specifications......................................................................................................6
3.1. Electrical Characteristics ................................................................................................6
3.2. Thermal Conditions ...................................................................................................... 29
3.3. Absolute Maximum Ratings..........................................................................................29
4. Precision32™ SiM3C1xx System Overview .................................................................... 32
4.1. Power ........................................................................................................................... 34
4.1.1. LDO and Voltage Regulator (VREG0) ................................................................. 34
4.1.2. Voltage Supply Monitor (VMON0) ....................................................................... 34
4.1.3. External Regulator (EXTVREG0) ........................................................................ 34
4.1.4. Power Management Unit (PMU).......................................................................... 34
4.1.5. Device Power Modes........................................................................................... 35
4.2. I/O................................................................................................................................. 36
4.2.1. General Features.................................................................................................36
4.2.2. High Drive Pins (PB4)..........................................................................................36
4.2.3. 5 V Tolerant Pins (PB3) ....................................................................................... 36
4.2.4. Crossbars ............................................................................................................ 36
4.3. Clocking........................................................................................................................ 37
4.3.1. PLL (PLL0)........................................................................................................... 38
4.3.2. Low Power Oscillator (LPOSC0) ......................................................................... 38
4.3.3. Low Frequency Oscillator (LFOSC0)................................................................... 38
4.3.4. External Oscillators (EXTOSC0).......................................................................... 38
4.4. Data Peripherals...........................................................................................................39
4.4.1. 16-Channel DMA Controller................................................................................. 39
4.4.2. 128/192/256-bit Hardware AES Encryption (AES0) ............................................ 39
4.4.3. 16/32-bit CRC (CRC0)......................................................................................... 39
4.5. Counters/Timers and PWM ..........................................................................................40
4.5.1. Programmable Counter Array (EPCA0, PCA0, PCA1)........................................ 40
4.5.2. 32-bit Timer (TIMER0, TIMER1).......................................................................... 40
4.5.3. Real-Time Clock (RTC0) ..................................................................................... 41
4.5.4. Low Power Timer (LPTIMER0)............................................................................41
4.5.5. Watchdog Timer (WDTIMER0)............................................................................41
4.6. Communications Peripherals ....................................................................................... 42
4.6.1. External Memory Interface (EMIF0).....................................................................42
4.6.2. USART (USART0, USART1)............................................................................... 42
4.6.3. UART (UART0, UART1) ...................................................................................... 42
4.6.4. SPI (SPI0, SPI1) .................................................................................................. 43
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Rev.1.0
SiM3C1xx
4.6.5. I2C (I2C0, I2C1)................................................................................................... 43
4.6.6. I2S (I2S0)............................................................................................................. 44
4.7. Analog .......................................................................................................................... 45
4.7.1. 12-Bit Analog-to-Digital Converters (SARADC0, SARADC1).............................. 45
4.7.2. Sample Sync Generator (SSG0) ......................................................................... 45
4.7.3. 10-Bit Digital-to-Analog Converter (IDAC0, IDAC1) ............................................ 45
4.7.4. 16-Channel Capacitance-to-Digital Converter (CAPSENSE0) ............................ 46
4.7.5. Low Current Comparators (CMP0, CMP1) .......................................................... 46
4.7.6. Current-to-Voltage Converter (IVC0) ................................................................... 46
4.8. Reset Sources..............................................................................................................47
4.9. Security ........................................................................................................................ 48
4.10.On-Chip Debugging ..................................................................................................... 48
5. Ordering Information .........................................................................................................49
6. Pin Definitions and Packaging Information.....................................................................51
6.1. SiM3C1x7 Pin Definitions............................................................................................. 51
6.2. SiM3C1x6 Pin Definitions............................................................................................. 59
6.3. SiM3C1x4 Pin Definitions............................................................................................. 66
6.4. LGA-92 Package Specifications...................................................................................70
6.4.1. LGA-92 Solder Mask Design ............................................................................... 72
6.4.2. LGA-92 Stencil Design ........................................................................................ 72
6.4.3. LGA-92 Card Assembly ....................................................................................... 72
6.5. TQFP-80 Package Specifications ................................................................................ 73
6.5.1. TQFP-80 Solder Mask Design............................................................................. 76
6.5.2. TQFP-80 Stencil Design ...................................................................................... 76
6.5.3. TQFP-80 Card Assembly..................................................................................... 76
6.6. QFN-64 Package Specifications .................................................................................. 77
6.6.1. QFN-64 Solder Mask Design............................................................................... 79
6.6.2. QFN-64 Stencil Design ........................................................................................ 79
6.6.3. QFN-64 Card Assembly....................................................................................... 79
6.7. TQFP-64 Package Specifications ................................................................................ 80
6.7.1. TQFP-64 Solder Mask Design............................................................................. 83
6.7.2. TQFP-64 Stencil Design ...................................................................................... 83
6.7.3. TQFP-64 Card Assembly..................................................................................... 83
6.8. QFN-40 Package Specifications .................................................................................. 84
6.8.1. QFN-40 Solder Mask Design............................................................................... 86
6.8.2. QFN-40 Stencil Design ........................................................................................ 86
6.8.3. QFN-40 Card Assembly....................................................................................... 86
7. Revision Specific Behavior............................................................................................... 87
7.1. Revision Identification .................................................................................................. 87
7.2. Comparator Rising/Falling Edge Flags in Debug Mode (CMP0, CMP1)...................... 88
7.2.1. Problem ...............................................................................................................88
7.2.2. Impacts ................................................................................................................ 88
7.2.3. Workaround ......................................................................................................... 88
7.2.4. Resolution............................................................................................................ 88
Document Change List ........................................................................................................... 89
Contact Information ................................................................................................................ 90
Rev.1.0
3
SiM3C1xx
1. Related Documents and Conventions
1.1. Related Documents
This data sheet accompanies several documents to provide the complete description of the SiM3C1xx device
family.
1.1.1. SiM3U1xx/SiM3C1xx Reference Manual
The Silicon Laboratories SiM3U1xx/SiM3C1xx Reference Manual provides detailed functional descriptions for the
SiM3C1xx devices.
1.1.2. Hardware Access Layer (HAL) API Description
The Silicon Laboratories Hardware Access Layer (HAL) API provides C-language functions to modify and read
each bit in the SiM3C1xx devices. This description can be found in the SiM3xxxx HAL API Reference Manual.
1.1.3. ARM Cortex-M3 Reference Manual
The ARM-specific features like the Nested Vector Interrupt Controller are described in the ARM Cortex-M3
reference documentation. The online reference manual can be found here:
http://infocenter.arm.com/help/topic/com.arm.doc.subset.cortexm.m3/index.html#cortexm3.
1.2. Conventions
The block diagrams in this document use the following formatting conventions:
Internal Module
Other Internal
Peripheral Block
External Memory
Block
DMA Block
Memory Block
External to MCU
Block
Input_Pin
Functional Block
Internal_Input_Signal
Output_Pin
Internal_Output_Signal
REGn_NAME / BIT_NAME
Figure 1.1. Block Diagram Conventions
4
Rev.1.0
SiM3C1xx
2. Typical Connection Diagrams
This section provides typical connection diagrams for SiM3C1xx devices.
2.1. Power
Figure 2.1 shows a typical connection diagram for the power pins of the SiM3C1xx devices when the internal
regulator is in use.
SiM3C1xx Device
5 V (in)
VREGn
3.3 V (out)
VREGIN
VIOHD
VDD
VIO
1 uF and 0.1 uF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
VSS
VSSHD
Figure 2.1. Connection Diagram with Voltage Regulator Used
Figure 2.2 shows a typical connection diagram for the power pins of the SiM3C1xx devices when the internal
regulator is not used.
SiM3C1xx Device
1.8-3.6 V (in)
VREGn
VREGIN
VIOHD
1 uF and 0.1 uF bypass
capacitors required for
each power pin placed
as close to the pins as
possible.
VDD
VIO
VSS
VSSHD
Figure 2.2. Connection Diagram with Voltage Regulator Not Used
Rev.1.0
5
FPGA/CPLD
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