ADM1067ASU-REEL7 datasheet, PDF

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ADM1067ASU-REEL7: DescriptionSuper Sequencer with Open-Loop Margining DACs; File Size472KB，31 Pages; ManufacturerADI; Websitehttps://www.analog.com

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ADM1067ASU-REEL7 Overview

Super Sequencer with Open-Loop Margining DACs

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Data Sheet

FEATURES

Complete supervisory and sequencing solution for up to

10 supplies

10 supply fault detectors enable supervision of supplies to

<0.5% accuracy at all voltages at 25°C

<1.0% accuracy across all voltages and temperatures

5 selectable input attenuators allow supervision of supplies to

14.4 V on VH

6 V on VP1 to VP4 (VPx)

5 dual-function inputs, VX1 to VX5 (VXx)

High impedance input to supply fault detector with

thresholds between 0.573 V and 1.375 V

General-purpose logic input

10 programmable driver outputs, PDO1 to PDO10 (PDOx)

Open-collector with external pull-up

Push/pull output, driven to VDDCAP or VPx

Open collector with weak pull-up to VDDCAP or VPx

Internally charge-pumped high drive for use with external

N-FET (PDO1 to PDO6 only)

Sequencing engine (SE) implements state machine control of

PDO outputs

State changes conditional on input events

Enables complex control of boards

Power-up and power-down sequence control

Fault event handling

Interrupt generation on warnings

Watchdog function can be integrated in SE

Program software control of sequencing through SMBus

Open-loop margining solution for 6 voltage rails

6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage

adjustment via dc-to-dc converter trim/feedback node

Device powered by the highest of VPx, VH for improved

redundancy

User EEPROM: 256 bytes

Industry-standard 2-wire bus interface (SMBus)

Guaranteed PDO low with VH, VPx = 1.2 V

Available in 40-lead, 6 mm × 6 mm LFCSP and

48-lead, 7 mm × 7 mm TQFP packages

Super Sequencer with

Open-Loop Margining DACs

ADM1067

FUNCTIONAL BLOCK DIAGRAM

REFOUT REFGND SDA SCL A1

ADM1067

VREF

SMBus

INTERFACE

EEPROM

VX1

VX2

VX3

VX4

VX5

DUAL-

FUNCTION

INPUTS

(LOGIC INPUTS

SFDs)

SEQUENCING

ENGINE

CONFIGURABLE

OUTPUT

DRIVERS

(HV CAPABLE OF

DRIVING GATES

OF N-FET)

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

VP1

VP2

VP3

VP4

AGND

VDDCAP

VDD

ARBITRATOR

PROGRAMMABLE

RESET

GENERATORS

(SFDs)

CONFIGURABLE

OUTPUT

DRIVERS

(LV CAPABLE

OF DRIVING

LOGIC SIGNALS)

PDO7

PDO8

PDO9

PDO10

PDOGND

GND

VCCP

MDN

MUP

OUT

DAC

OUT

DAC

OUT

DAC

OUT

DAC

OUT

DAC

OUT

DAC

04635-001

DAC1

DAC2

DAC3

DAC4

DAC5

DAC6

Figure 1.

GENERAL DESCRIPTION

The

ADM1067

Super Sequencer® is a configurable supervisory/

sequencing device that offers a single-chip solution for supply

monitoring and sequencing in multiple supply systems. In addition

to these functions, the

ADM1067

integrates six 8-bit voltage

output DACs. These circuits can be used to implement an open-

loop margining system that enables supply adjustment by altering

either the feedback node or reference of a dc-to-dc converter

using the DAC outputs.

For more information about the

ADM1067

to the

AN-698 Application Note.

APPLICATIONS

Central office systems

Servers/routers

Multivoltage system line cards

DSP/FPGA supply sequencing

In-circuit testing of margined supplies

Rev. E

Document Feedback

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

ADM1067

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Detailed Block Diagram .................................................................. 4

Specifications..................................................................................... 5

Absolute Maximum Ratings............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution .................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 11

Powering the ADM1067 ................................................................ 14

Slew Rate Consideration............................................................ 14

Inputs................................................................................................ 15

Supply Supervision ..................................................................... 15

Programming the Supply Fault Detectors ............................... 15

Input Comparator Hysteresis .................................................... 15

Input Glitch Filtering ................................................................. 16

Supply Supervision with VXx Inputs ....................................... 16

VXx Pins as Digital Inputs ........................................................ 16

Outputs ............................................................................................ 17

Supply Sequencing Through Configurable Output Drivers ....... 17

Default Output Configuration .................................................. 17

Sequencing Engine ......................................................................... 18

Data Sheet

Overview ..................................................................................... 18

Warnings...................................................................................... 18

SMBus Jump (Unconditional Jump)........................................ 18

Sequencing Engine Application Example ............................... 19

Fault and Status Reporting ........................................................ 20

Supply Margining ........................................................................... 21

Overview ..................................................................................... 21

Open-Loop Supply Margining ................................................. 21

Writing to the DACs .................................................................. 21

Choosing the Size of the Attenuation Resistor ....................... 22

DAC Limiting and Other Safety Features ............................... 22

Applications Diagram .................................................................... 23

Communicating with the ADM1067 ........................................... 24

Configuration Download at Power-Up ................................... 24

Updating the Configuration ..................................................... 24

Updating the Sequencing Engine ............................................. 25

Internal Registers........................................................................ 25

EEPROM ..................................................................................... 25

Serial Bus Interface..................................................................... 25

SMBus Protocols for RAM and EEPROM .............................. 28

Write Operations ........................................................................ 28

Read Operations ......................................................................... 30

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 31

Rev. E | Page 2 of 31

Data Sheet

REVISION HISTORY

1/15—Rev. D to Rev. E

Changes to Figure 3, Figure 4, and Table 4 .................................... 9

Added Slew Rate Consideration Section......................................14

Added SCL Held Low Timeout Section and False Start

Detection Section ............................................................................26

Updated Outline Dimensions ........................................................31

Changes to Ordering Guide ...........................................................31

6/11—Rev. C to Rev. D

Changes to Serial Bus Timing Parameter in Table 1 .................... 5

Change to Figure 3 ............................................................................ 9

Added Exposed Pad Notation to Outline Dimensions ..............31

Changes to Ordering Guide ...........................................................31

5/08—Rev. B to Rev. C

Changes to Figure 1........................................................................... 1

Changes to Table 1 ............................................................................ 4

Changes to Powering the ADM1067 Section ..............................13

Changes to Sequence Detector Section ........................................18

Changes to Figure 27 ......................................................................20

Changes to Configuration Download at Power-Up Section .....23

Changes to Table 10 ........................................................................24

Changes to Figure 40 and Error Correction Section ..................29

Changes to Ordering Guide ...........................................................30

ADM1067

11/06—Rev. A to Rev. B

Updated Format ................................................................. Universal

Changes to Features .......................................................................... 1

Changes to Figure 2 .......................................................................... 3

Changes to Table 1 ............................................................................ 4

Changes to Table 2 ............................................................................ 7

Changes to Absolute Maximum Ratings Section ......................... 9

Changes to Programming the Supply Fault Detectors Section ... 14

Changes to Table 6 .......................................................................... 14

Added the Default Output Configuration Section ..................... 18

Changes to Fault Reporting Section ............................................. 21

Changes to Figure 28 ...................................................................... 24

Changes to the Identifying the ADM1067

on the SMBus Section ..................................................................... 26

Changes to Figure 30 and Figure 31 ............................................. 28

Changes to Ordering Guide ........................................................... 32

1/05—Rev. 0 to Rev. A

Changes to Figure 1 .......................................................................... 1

Changes to Absolute Maximum Ratings Section ......................... 8

Change to Supply Sequencing through Configurable

Output Drivers Section .................................................................. 16

Changes to Figure 28 ...................................................................... 22

Change to Table 9 ............................................................................ 25

10/04—Revision 0: Initial Version

Rev. E | Page 3 of 31

ADM1067ASU-REEL7 Related Products

	ADM1067ASU-REEL7	ADM1067	ADM1067ACP-REEL	ADM1067ACP-REEL7	ADM1067ASUZ1	ADM1067ASU-REEL	EVAL-ADM1067TQEBZ
Description	Super Sequencer with Open-Loop Margining DACs	Super Sequencer with Open-Loop Margining DACs	Super Sequencer with Open-Loop Margining DACs	Super Sequencer with Open-Loop Margining DACs	Super Sequencer with Open-Loop Margining DACs	Super Sequencer with Open-Loop Margining DACs	BOARD EVALUATION FOR ADM1067TQ

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