Data Sheet
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP4 (VPx)
5 dual-function inputs, VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Open-loop margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage
adjustment via dc-to-dc converter trim/feedback node
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and
48-lead, 7 mm × 7 mm TQFP packages
Super Sequencer with
Open-Loop Margining DACs
ADM1067
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND SDA SCL A1
A0
ADM1067
VREF
SMBus
INTERFACE
EEPROM
VX1
VX2
VX3
VX4
VX5
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
VP1
VP2
VP3
VP4
VH
AGND
VDDCAP
VDD
ARBITRATOR
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO7
PDO8
PDO9
PDO10
PDOGND
GND
VCCP
MDN
MUP
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
04635-001
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
Figure 1.
GENERAL DESCRIPTION
The
ADM1067
Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the
ADM1067
integrates six 8-bit voltage
output DACs. These circuits can be used to implement an open-
loop margining system that enables supply adjustment by altering
either the feedback node or reference of a dc-to-dc converter
using the DAC outputs.
For more information about the
ADM1067
register map, refer
to the
AN-698 Application Note.
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
Rev. E
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ADM1067
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 3
Detailed Block Diagram .................................................................. 4
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Powering the ADM1067 ................................................................ 14
Slew Rate Consideration............................................................ 14
Inputs................................................................................................ 15
Supply Supervision ..................................................................... 15
Programming the Supply Fault Detectors ............................... 15
Input Comparator Hysteresis .................................................... 15
Input Glitch Filtering ................................................................. 16
Supply Supervision with VXx Inputs ....................................... 16
VXx Pins as Digital Inputs ........................................................ 16
Outputs ............................................................................................ 17
Supply Sequencing Through Configurable Output Drivers ....... 17
Default Output Configuration .................................................. 17
Sequencing Engine ......................................................................... 18
Data Sheet
Overview ..................................................................................... 18
Warnings...................................................................................... 18
SMBus Jump (Unconditional Jump)........................................ 18
Sequencing Engine Application Example ............................... 19
Fault and Status Reporting ........................................................ 20
Supply Margining ........................................................................... 21
Overview ..................................................................................... 21
Open-Loop Supply Margining ................................................. 21
Writing to the DACs .................................................................. 21
Choosing the Size of the Attenuation Resistor ....................... 22
DAC Limiting and Other Safety Features ............................... 22
Applications Diagram .................................................................... 23
Communicating with the ADM1067 ........................................... 24
Configuration Download at Power-Up ................................... 24
Updating the Configuration ..................................................... 24
Updating the Sequencing Engine ............................................. 25
Internal Registers........................................................................ 25
EEPROM ..................................................................................... 25
Serial Bus Interface..................................................................... 25
SMBus Protocols for RAM and EEPROM .............................. 28
Write Operations ........................................................................ 28
Read Operations ......................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
Rev. E | Page 2 of 31
Data Sheet
REVISION HISTORY
1/15—Rev. D to Rev. E
Changes to Figure 3, Figure 4, and Table 4 .................................... 9
Added Slew Rate Consideration Section......................................14
Added SCL Held Low Timeout Section and False Start
Detection Section ............................................................................26
Updated Outline Dimensions ........................................................31
Changes to Ordering Guide ...........................................................31
6/11—Rev. C to Rev. D
Changes to Serial Bus Timing Parameter in Table 1 .................... 5
Change to Figure 3 ............................................................................ 9
Added Exposed Pad Notation to Outline Dimensions ..............31
Changes to Ordering Guide ...........................................................31
5/08—Rev. B to Rev. C
Changes to Figure 1........................................................................... 1
Changes to Table 1 ............................................................................ 4
Changes to Powering the ADM1067 Section ..............................13
Changes to Sequence Detector Section ........................................18
Changes to Figure 27 ......................................................................20
Changes to Configuration Download at Power-Up Section .....23
Changes to Table 10 ........................................................................24
Changes to Figure 40 and Error Correction Section ..................29
Changes to Ordering Guide ...........................................................30
ADM1067
11/06—Rev. A to Rev. B
Updated Format ................................................................. Universal
Changes to Features .......................................................................... 1
Changes to Figure 2 .......................................................................... 3
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 7
Changes to Absolute Maximum Ratings Section ......................... 9
Changes to Programming the Supply Fault Detectors Section ... 14
Changes to Table 6 .......................................................................... 14
Added the Default Output Configuration Section ..................... 18
Changes to Fault Reporting Section ............................................. 21
Changes to Figure 28 ...................................................................... 24
Changes to the Identifying the ADM1067
on the SMBus Section ..................................................................... 26
Changes to Figure 30 and Figure 31 ............................................. 28
Changes to Ordering Guide ........................................................... 32
1/05—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Absolute Maximum Ratings Section ......................... 8
Change to Supply Sequencing through Configurable
Output Drivers Section .................................................................. 16
Changes to Figure 28 ...................................................................... 22
Change to Table 9 ............................................................................ 25
10/04—Revision 0: Initial Version
Rev. E | Page 3 of 31
ADM1067
Supply margining can be performed with a minimum of external
components. The margining capability can be used for in-circuit
testing of a board during production (for example, to verify
board functionality at −5% of nominal supplies), or it can be
used dynamically to accurately control the output voltage of
a dc-to-dc converter.
The device also provides up to 10 programmable inputs for
monitoring undervoltage faults, overvoltage faults, or out-of-
window faults on up to 10 supplies. In addition, 10 program-
mable outputs can be used as logic enables.
Data Sheet
Six of these programmable outputs can also provide up to a 12 V
output for driving the gate of an N-FET that can be placed in
the path of a supply.
The logical core of the device is a sequencing engine. This state-
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
DETAILED BLOCK DIAGRAM
REFOUT
REFGND
SDA SCL A1
A0
OSC
EEPROM
VREF
SMBus
INTERFACE
DEVICE
CONTROLLER
ADM1067
VX1
VX2
VX3
VX4
GPI SIGNAL
CONDITIONING
SFD
CONFIGURABLE
OUTPUT DRIVER
(HV)
PDO1
PDO2
PDO3
GPI SIGNAL
CONDITIONING
CONFIGURABLE
OUTPUT DRIVER
(HV)
VX5
VP1
VP2
VP3
VP4
VH
AGND
VDDCAP
VDD
ARBITRATOR
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
SFD
SFD
SEQUENCING
ENGINE
PDO4
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO5
PDO6
PDO7
PDO8
SFD
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO9
PDO10
MDN
MUP
VCCP
REG 5.25V
CHARGE PUMP
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
V
OUT
DAC
PDOGND
GND
04635-002
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
Figure 2.
Rev. E | Page 4 of 31
Data Sheet
SPECIFICATIONS
VH = 3.0 V to 14.4 V
1
, VPx = 3.0 V to 6.0 V
1
, T
A
= −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPx
VPx
VH
VDDCAP
C
VDDCAP
POWER SUPPLY
Supply Current, I
VH
, I
VPx
Additional Currents
All PDO FET Drivers On
Current Available from VDDCAP
DACs Supply Current
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPx Pins
Input Impedance
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VXx Pins
Input Impedance
Detection Ranges
Ultralow Range
Absolute Accuracy
Threshold Resolution
Digital Glitch Filter
BUFFERED VOLTAGE OUTPUT DACs
Resolution
Code 0x80 Output Voltage
Range 1
Range 2
Range 3
Range 4
Output Voltage Range
LSB Step Size
0.592
0.796
0.997
1.247
2.2
1
10
Min
3.0
6.0
14.4
5.4
Typ
Max
Unit
V
V
V
V
μF
mA
mA
2
mA
mA
mA
mA
Test Conditions/Comments
ADM1067
2.7
10
4.75
Minimum supply required on one of VH, VPx
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off
VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO10 off
Maximum additional load that can be drawn from all PDO
pull-ups to VDDCAP
Six DACs on with 100 μA maximum load on each
Running round-robin loop
1 ms duration only, VDDCAP = 3 V
4.2
1
6
52
±0.05
6
2.5
52
±0.05
2.5
1.25
0.573
1
0.573
1.375
±1
8
0
100
8
6
3
1.375
14.4
6
kΩ
%
V
V
kΩ
%
V
V
V
MΩ
V
%
Bits
μs
μs
Bits
Midrange and high range
Low range and midrange
No input attenuation error
No input attenuation error
VREF error + DAC nonlinearity + comparator offset error +
input attenuation error
Minimum programmable filter length
Maximum programmable filter length
Six DACs are individually selectable for centering on one of
four output voltage ranges
0.6
0.8
1
1.25
601.25
2.36
0.603
0.803
1.003
1.253
V
V
V
V
mV
mV
Same range, independent of center point
Rev. E | Page 5 of 31
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