PI2EQX4401
2.5Gbps x1 Lane Serial PCI Express
Repeater/Equalizer with Clock Buffer
Features
•
•
•
•
•
•
•
•
•
•
One high-speed PCI Express lane
Adjustable Transmiter De-Emphasis & Amplitude
Adjustable Receiver Equalization
One Spread Spectrum Reference Clock Buffer Output
100Ω Differential CML I/O’s
Low Power (100mW per Channel)
Stand-by Mode – Power Down State
V
CC
Operating Range: 1.8V ±0.1V
Built in Clock Buffer
Packaging (Pb-free & Green):
— 36-pad TQFN (ZF36)
Description
Pericom Semiconductor’s PI2EQX4401 is a low power, PCI-
Express compliant signal re-driver. The device provides
programmable equalization, amplification, and de-emphasis
by using 4 select bits, SEL[0:3], to optimize performance
over a variety of physical mediums by reducing Inter-symbol
interference. PI2EQX4401 supports two 100 Differential CML
data I/O’s between the Protocol ASIC to a switch fabric, across
a backplane, or extends the signals across other distant data
pathways on the user’s platform.
The integrated equalization circuitry provides flexibility with
signal integrity of the PCI Express signal before the re-driver.
Whereas the integrated de-emphasis circuitry provides flexibility
with signal integrity of the PCI Express signal after the re-driver.
In addition to providing signal re-conditioning, Pericom’s
PI2EQX4401 also provides power management Stand-by mode
operated by a Bus Enable pin.
Block Diagram
Pin Description
SEL0_A
SEL1_A
SEL2_A
SEL3_A
½½½½½½
36
35
34
33
32
31
EN_A
30
NC
NC
VDD
½½½
½½½
EN_B
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
VDD
A0+
A0-
GND
AGND
VDD
BI+
BI-
GND
IREF
AI+
½½½
½½½
½½½½½½½½½
½½½½½½½½
½½½
AI-
GND
½½½
½½½½½½½½½
½½½
AVDD
VDD
GND
24
23
22
21
20
19
½½½½½½½½½
½½½½½½½½½½½½½½½½½½½½½½
½½½½½½½½½
B0+
B0-
GND
½½½½½
½½½½½
½½½½½½
½½½
½½½½½
½½½½½
VDD
CLKIN+
CLKIN-
SEL0_B
SEL1_B
SEL2_B
SEL3_B
OUT+
OUT-
½½½½
1
PS8777B
02/15/06
PI2EQX4401
2.5Gbps x1 Lane Serial PCI Express
Repeater/Equalizer with Clock Buffer
Pin Description
Pin #
1, 6, 10, 23, 28
2
3
4, 9, 20, 25
22
21
33, 34
13, 14
32
15
31
16
27
26
7
8
30, 29
12
11
17, 18
5
24
19
35, 36
Pin Name
V
DD
AI+
AI-
GND
BI+
BI-
SEL[0:1]_A
SEL[0:1]_B
SEL[2]_A
SEL[2]_B
SEL[3]_A
SEL[3]_B
AO+
AO-
BO+
BO-
EN_[A,B]
CLKIN-
CLKIN+
OUT+, OUT-
AVDD
AGND
IREF
NC
I/O
PWR
I
I
PWR
I
I
I
I
I
I
I
I
O
O
O
O
I
I
I
O
PWR
PWR
O
N/A
Description
1.8V Supply Voltage
Positive CML Input Channel A with internal 50Ω pull down
Negative CML Input Channel A with internal 50Ω pull down
Supply Ground
Positive CML Input Channel B with internal 50Ω pull down
Negative CML Input Channel B with internal 50Ω pull down
Selection pins for equalizer (see Amplifier Configuration Table)
w/ 50KΩ internal pull up
Selection pins for amplifier (see Amplifier Configuration Table)
w/ 50KΩ internal pull up
Selection pins for De-Emphasis (See De-Emphasis Configuration Table)
w/ 50KΩ internal pull up
Positive CML Output Channel A internal 50Ω pull up during normal operation and
2KΩ pull up otherwise.
Negative CML Output Channel A with internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
Positive CML Output Channel B with internal 50Ω pull up during normal operation
and 2KΩ pull up otherwise.
Negative CMLOutput Channel B with internal 50Ω pull up during normal opera-
tion and 2KΩ pull up otherwise.
EN_[A:B] is the enable pin. A LVCMOS high provides normal operation. A LVC-
MOS low selects a low power down mode.
Differential Input Reference Clock
Differential Reference Clock Output
1.8V Analog supply voltage
Analog ground
External 475Ω resistor connection to set the differential output current
No connect pins. For normal operation, leave pins floating
2
PS8777B
02/15/06
PI2EQX4401
2.5Gbps x1 Lane Serial PCI Express
Repeater/Equalizer with Clock Buffer
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Storage Temperature........................................................ –65°C to +150°C
Supply Voltage to Ground Potential ................................... –0.5V to +2.5V
DC SIG Voltage.......................................................... –0.5V to V
CC
+0.5V
Current Output ................................................................-25mA to +25mA
Power Dissipation Continous ......................................................... 500mW
Operating Temperature.............................................................. 0 to +70°C
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Output Swing Control
SEL2_[A:B]
0
1
Swing
1x
1.2x
Output De-emphasis Adjustment
SEL3_[A:B]
0
1
De-emphasis
0dB
-3.5dB
Equalizer Selection
SEL0_[A:B]
0
0
1
1
SEL1_[A:B]
0
1
0
1
Compliance Channel
no equalization
[0:2.5dB] @ 1.25 GHz
[2.5:4.5dB] @ 1.25 GHz
[4.5:6.5dB] @ 1.25 GHz
3
PS8777B
02/15/06
PI2EQX4401
2.5Gbps x1 Lane Serial PCI Express
Repeater/Equalizer with Clock Buffer
AC/DC Electrical Characteristics
(V
DD
= 1.8 ±0.1V)
Symbol
Ps
Parameter
Supply Power
Latency
CML Receiver Input
RL
RX
Return Loss
Differential Input Peak-to-
V
RX-DIFFP-P
peak Voltage
AC Peak Common Mode
V
RX-CM-ACP
Input Voltage
DC Differential Input
Z
RX-DIFF-DC
Impedance
Z
RX-DC
DC Input Impedance
Equalization
J
RS
J
RM
Residual Jitter
(1,2)
Random Jitter
(1,2)
Total Jitter
Deterministic jitter
1.5
0.3
0.2
Ulp-p
psrms
Conditions
EN = LVCMOS Low
EN = LVCMOS High
From input to output
Min.
Typ.
Max.
0.1
0.3
Units
W
ns
2.0
50 MHz to 1.25 GHz
0.175
12
1.200
150
80
40
100
50
120
60
dB
V
mV
Ω
Notes
1. K28.7 pattern is applied differentially at point A as shown in Figure 1.
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum
deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or
equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or
its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at
0V at point C of Figure 1.
½½½
½½½½½½½
½½½½½½
½
½
½½½½½½½
½½½½½½½½½½
½½½
½½½½½½½½½
½½
½½
½½½
½½½½½½½½½
½½
½½½
½
Figure 1. Test Condition Referenced in the Electrical Characteristic Table
4
PS8777B
02/15/06
PI2EQX4401
2.5Gbps x1 Lane Serial PCI Express
Repeater/Equalizer with Clock Buffer
AC/DC Electrical Characteristics
(T
A
= 0 to 70˚C)
Symbol
Parameter
Conditions
Differential Swing
| V
TX-D+
- V
TX-D-
|
| V
TX-D+
+ V
TX-D-
| / 2
20% to 80%
(1)
Single ended
40
80
75
V
TX-DIFFP-P
= 2 * | V
TX-D+
- V
TX-D-
|
0.8
50
100
Min.
Typ.
Max.
Units
CML Transmitter Output (100Ω differential)
V
DIFFP
V
TX-C
t
F
, t
R
Z
OUT
Z
TX-DIFF-DC
C
TX
V
TX-DIFFP-P
Output Voltage Swing
Common-Mode Voltage
Transition Time
Output resistance
DC Differential TX Impedance
AC Coupling Capacitor
Differential Peak-to-peak Ouput
Voltage
400
V
CC
-
0.3
150
60
120
200
1.8
ps
Ω
Ω
nF
V
900
mVp-p
LVCMOS Control Pins
V
IH
V
IL
I
IH
I
IL
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
0.65 ×
V
DD
0.35 ×
V
DD
250
500
V
µA
Note:
1. Using K28.7 (0011111000) pattern)
5
PS8777B
02/15/06
Mobile and portable
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