PI6C410B
Clock Generator for Intel
PCI-Express Server
Chipset
Features
•
•
•
•
•
14.318 MHz Crystal Input
Selectable of 100, 133, 166, 200, 266, 333, and 400 MHz
CPU Output Frequencies
SMBus: Power Management Control
Spread Spectrum support (-0.5% down spread)
Packaging (Pb-free & Green):
—56-Pin SSOP (V)
—56-Pin TSSOP (A)
Description
PI6C410B is a high-speed, low-noise clock generator designed to
work with Intel Server PCI-Express Chipset. The Spread Spectrum
PLL based clock generator reduces EMI emission and supports a
wide range of frequencies.
Jitter Performance
•
•
•
•
•
< 85ps Cycle-to-Cycle CPU clock jitter
< 350ps Cycle-to-Cycle 48MHz clock jitter
< 500ps Cycle-to-Cycle PCI clock jitter
< 125ps Cycle-to-Cycle SRC clock jitter
< 1000ps Cycle-to-Cycle REF clock jitter
Output Features
•
•
•
•
•
Four Pairs of Differential CPU Clocks
Five Pairs of SRC Clocks
Seven PCI Clocks
One 48 MHz USB clock
Two REF clocks
Skew Performance
• < 100ps Output to output CPU clock skew
• < 500ps Output to output PCI clock skew
• < 250ps Output to output SRC clock skew
Block Diagram
XT AL_IN
XT AL_OUT
XT AL
OSC
PLL 1
SDA
SCL
FS_A
FS_B/TEST_MODE
FS_C/TEST_SEL
VTT_PWRGD#
/PWRDWN
IREF
CONTROL
SM Bus
Logic
DIV
PLL 2
USB_48
Pin Configuration
VDD_PCI
VSS_PCI
PCI_0
PCI_1
PCI_2
PCI_3
VSS_PCI
VDD_PCI
PCIF_0
PCIF_1
PCIF_2
VDD_48
USB_48
VSS_48
VDD_SRC
SRC_0
SRC_0#
SRC_1#
SRC_1
VSS_SRC
SRC_2
SRC_2#
SRC_3#
SRC_3
VDD_SRC
SRC_4
SRC_4#
VDD_SRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF [0:1]
PCI [0:3]
PCIF [0:2]
DIV
SRC [0:4]
SRC [0:4]#
CPU [0:3]
CPU [0:3]#
DIV
FS_C / TEST_SEL
REF_0
REF_1
VDD_REF
XTAL_IN½
XTAL_OUT
VSS_REF
FS_B/TEST_MODE
FS_A
VDD_CPU
CPU_0
CPU_0#
VDD_CPU
CPU_1
CPU_1#
VSS_CPU
CPU_2
CPU_2#
VDD_CPU
CPU_3
CPU_3#
VDD_A
VSS_A
IREF
NC
VTT_PWRGD# / PWRDWN
SDA
SCL
1
PS8811A
02/01/06
PI6C410B
Clock Generator for Intel PCI-Express Server Chipset
Pin Descriptions
Pin Name
REF[0:1]
XTAL_IN
XTAL_OUT
CPU[0:3] & CPU[0:3]#
SRC[0:4] & SRC[0:4]#
PCIF[0:2]
PCI[0:3]
USB_48
FS_A
FS_B / TEST_MODE
FS_C / TEST_SEL
IREF
VTT_PWRGD# /
PWRDWN
SDA
SCL
V
DD_PCI
V
DD_48
V
DD_SRC
V
DD_CPU
V
DD_REF
V
SS_PCI
V
SS_48
V
SS_SRC
V
SS_CPU
V
SS_REF
V
DD_A
V
SS_A
Type
Output
Input
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
I/O
Input
Power
Power
Power
Power
Power
Ground
Ground
Ground
Ground
Ground
Power
Ground
Pin No
54, 55
52
51
36, 37; 39, 40; 42,
43; 45, 46
16, 17; 18, 19; 21, 22;
23, 24; 26, 27
9, 10, 11
3, 4, 5, 6
13
48
49
56
33
31
30
29
1, 8
12
15, 25, 28
38, 44, 47
53
2, 7
14
20
41
50
35
34
Descriptions
3.3V 14.31818 MHz outputs
14.31818 MHz crystal input
14.31818 MHz crystal output
Differential CPU outputs
Differential Serial Reference Clock outputs
33 MHz clocks outputs (free running)
33 MHz clocks outputs
48 MHz clock output
3.3V LVTTL inputs for CPU frequency selection
3.3V LVTTL inputs for CPU frequency selection / Test Mode
select: 0 = Hi-Z, 1 = Ref/N
3.3V LVTTL inputs for CPU frequency selection / Test Mode
select if pulled to 3.3V when Vtt_Pwrgd# is asserted LOW
External resistor connection for internal current reference
3.3V LVTTL Level sensitive strobe used to determine to latch the
FS_A, FS_B/TEST_MODE and FS_C/TEST_SEL inputs (active
low) / 3.3V LVTTL active high input for Power Down operation.
SMBus compatible SDATA
SMBus compatible SCLOCK
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
3.3V Power Supply for Outputs
Ground for Outputs
Ground for Outputs
Ground for Outputs
Ground for Outputs
Ground for Outputs
3.3V Power Supply for PLL
Ground for PLL
2
PS8811A
02/01/06
PI6C410B
Clock Generator for Intel PCI-Express Server Chipset
Functionality
Frequency Selection
FS_C
1
0
0
0
0
1
1
1
FS_B
0
0
1
1
0
0
1
1
FS_A
1
1
1
0
0
0
0
1
CPU
100 MHz
133 MHz
166 MHz
200 MHz
266 MHz
333 MHz
400 MHz
Reserved
SRC
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
PCIF / PCI
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
REF
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
USB_48
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Note
1
1
1
1
1
1
1
1
Notes:
1. Refer to DC Electrical Characteristics for FS_A, FS_B and FS_C (Vih_FS, Vil_FS) threshold levels
Test Mode Selection
TEST_MODE
1
0
Notes:
2.
Test mode will occur where the SMBus Bit 6 of Byte 6 = 1, or FS_C/TEST_SEL is set to logic high level.
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
PCIF / PCI
REF/N
Hi-Z
REF
REF
Hi-Z
USB_48
REF/N
Hi-Z
Note
2
2
PWRDWN Functionality
PWRDWN
0
1
CPU
Normal
Iref × 2 or
Float
CPU#
Normal
Float
SRC
Normal
Iref × 2 or
Float
SRC#
Normal
Float
PCIF / PCI
33 MHz
Low
REF
14.318 MHz
Low
USB_48
48 MHz
Low
3
PS8811A
02/01/06
PI6C410B
Clock Generator for Intel PCI-Express Server Chipset
Serial Data Interface (SMBus)
PI6C410B is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
0/1
Data Protocol
1 bit
Start
bit
7 bits
Slave
Addr
1
R/W
1
Ack
8 bits
Register
offset
1
Ack
8 bits
Byte
Count = N
1
Ack
8 bits
Data Byte
0
1
Ack
…
8 bits
Data Byte
N-1
1
Ack
1 bit
Stop bit
Note:
1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
Data Byte 0: Control Register
Bit
0
1
2
3
4
5
6
7
Descriptions
SRC_0 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_1 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_2 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_3 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
SRC_4 Output Enable
1 = Enabled, 0 = Disabled (Hi-Z)
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power-Up
Condition
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
Output(s) Affected
SRC_0
SRC_1
SRC_2
SRC_3
SRC_4
Pin
17, 18
19, 20
22, 23
24, 25
26, 27
Source Pin
NA
NA
NA
NA
NA
4
PS8811A
02/01/06
PI6C410B
Clock Generator for Intel PCI-Express Server Chipset
Data Byte 1: Control Register
Bit
Descriptions
Type
Power-Up
Condition
Output(s) Affected
Pin
3, 4, 5, 6, 9, 10,
11, 16, 17, 18, 19,
21, 22, 23, 24, 26,
27, 36, 37, 39, 40,
42, 43, 45, 46
45, 46
42, 43
Source Pin
0
Spread Spectrum
1 = On, 0 = Off
CPU_0 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
CPU_1 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
Reserved
CPU_2 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
CPU_3 output enable
1 = Enabled, 0 = Disabled (Hi-Z)
REF0 Output Enable
1 = Enabled, 0 = Disabled
REF1 Output Enable
1 = Enabled, 0 = Disabled
RW
0 = Spread off
CPU[0:3], SRC[0:4],
PCI[0:3], PCIF[0:2]
NA
1
2
3
4
5
6
7
RW
RW
RW
RW
RW
RW
RW
1 = Enabled
1 = Enabled
CPU_0, CPU_0#
CPU_1, CPU_1#
NA
NA
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
CPU_2, CPU_2#
CPU_3, CPU_3#
REF_0
REF_1
39, 40
36, 37
55
54
NA
NA
NA
NA
Data Byte 2: Control Register
Bit
0
1
2
3
4
5
6
7
Descriptions
USB_48 Output Enable
1 = Enabled, 0 = Disabled
PCIF_0 Output Enable
1 = Enabled, 0 = Disabled
PCIF_1 Output Enable
1 = Enabled, 0 = Disabled
PCIF_2 Output Enable
1 = Enabled, 0 = Disabled
PCI_0 Output Enable
1 = Enabled, 0 = Disabled
PCI_1 Output Enable
1 = Enabled, 0 = Disabled
PCI _2 Output Enable
1 = Enabled, 0 = Disabled
PCI _3 Output Enable
1 = Enabled, 0 = Disabled
Type
RW
RW
RW
RW
RW
RW
RW
RW
Power-Up
Condition
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
1 = Enabled
Output(s) Affected
USB_48
PCIF_0
PCIF_1
PCIF_2
PCI_0
PCI_1
PCI_2
PCI_3
Pin
13
9
10
11
3
4
5
6
Source Pin
NA
NA
NA
NA
NA
NA
NA
NA
5
PS8811A
02/01/06
京公网安备 11010802033920号
EEWORLD
