Data Sheet
FEATURES
Supports DOCSIS 2.0 and EuroDOCSIS specifications for
reverse path transmission systems
Gain programmable in 1 dB steps over a 59 dB range
Low distortion at 61 dBmV output
−59 dBc SFDR at 21 MHz
−54 dBc SFDR at 65 MHz
Output noise level at minimum gain 1.3 nV/√Hz
Maintains 75 Ω output impedance in transmit-enable and
transmit-disable condition
Upper bandwidth of 100 MHz (full gain range)
3.3 V supply operation
Supports SPI® interfaces
V
IN+
DIFF
OR SINGLE
INPUT
AMP
VERNIER
3.3 V, Upstream,
Cable Line Driver
AD8324
FUNCTIONAL BLOCK DIAGRAM
BYP
V
OUT+
ATTENUATION
CORE
OUTPUT
STAGE
V
OUT–
8
DECODE
8
POWER-
DOWN LOGIC
RAMP
Z
OUT
DIFF =
75Ω
V
IN–
Z
IN
(SINGLE) = 550Ω
Z
IN
(DIFF) = 1100Ω
AD8324
DATA LATCH
8
04339-0-001
SHIFT
REGISTER
APPLICATIONS
DOCSIS 2.0 and EuroDOCSIS cable modems
CATV set-top boxes
CATV telephony modems
Coaxial and twisted pair line drivers
GND
DATEN SDATA
CLK
TXEN
SLEEP
Figure 1.
GENERAL DESCRIPTION
The
AD8324
is a low cost amplifier designed for coaxial line
driving. The features and specifications make the
AD8324
ideally suited for DOCSIS® 2.0 and EuroDOCSIS applications.
The gain of the
AD8324
is digitally controlled. An 8-bit serial
word determines the desired output gain over a 59 dB range,
resulting in gain changes of 1 dB/LSB.
The
AD8324
accepts a differential or single-ended input signal.
The output is specified for driving a 75 Ω load through a 1:1
transformer.
Distortion performance of –54 dBc is achieved with an output
level up to 61 dBmV at 65 MHz bandwidth.
This device has a sleep mode function that reduces the quiescent
current to 30 μA and a full power-down function that reduces
power-down current to 2.5 mA.
The
AD8324
is packaged in a low cost, 20-lead LFCSP and a
20-lead QSOP. The
AD8324
operates from a single 3.3 V supply.
–80
5
15
25
35
45
FREQUENCY (MHz)
55
65
–40
–50
DISTORTION (dBc)
V
OUT
= 61dBmV @ DEC 60
THIRD HARMONIC
–60
–70
V
OUT
= 61dBmV @ DEC 60
SECOND HARMONIC
04339-0-002
Figure 2. Worst Harmonic Distortion vs. Frequency
Rev. C
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AD8324
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Logic Inputs (TTL-/CMOS-Compatible Logic) ....................... 4
Timing Requirements .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuit ...................................................................................... 11
Applications Information .............................................................. 12
General Applications.................................................................. 12
Circuit Description..................................................................... 12
Data Sheet
Gain Programming for the AD8324 ........................................ 12
Input Bias, Impedance, and Termination................................ 12
Output Bias, Impedance, and Termination ............................ 12
Power Supply............................................................................... 13
Signal Integrity Layout Considerations ................................... 13
Initial Power-Up ......................................................................... 13
RAMP Pin and BYP Pin Features ............................................ 13
Power Saving Features ............................................................... 14
Distortion, Adjacent Channel Power, and DOCSIS .............. 14
Utilizing Diplex Filters............................................................... 14
Noise and DOCSIS ..................................................................... 14
Differential Signal Source.......................................................... 15
Differential Signal from Single-Ended Source ....................... 15
Single-Ended Source .................................................................. 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
5/16—Rev. B to Rev. C
Change CP-20-1 to CP-20-6.............................................. Universal
Changes to Figure 5, Figure 6, and Table 6 ................................... 7
Changes to Figure 23 ...................................................................... 13
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
7/13—Rev. A to Rev. B
Changes to General Description Section ...................................... 1
Changes to Table 6 ............................................................................ 7
Added Test Circuits Section .......................................................... 11
Changed Applications Section to Applications Information
Section .............................................................................................. 12
Changes to Output Bias, Impedance, and Termination Section .... 12
Deleted Evaluation Board Features and Operation Section ..... 13
Deleted Overshoot on PC Printer Ports Section, Installing
Visual Basic Control Software Section, Running AD8324
Software Section, Figure 27; Renumbered Sequentially,
Controlling Gain/Attenuation of the AD8324 Section,
Figure 28, Transmit Enable and Sleep Mode Section, and
Memory Functions Section ........................................................... 14
Changes to Distortion, Adjacent Channel Power, and DOCSIS
Section and Noise and DOCSIS Section ..................................... 14
Deleted Figure 29............................................................................ 15
Changes to Differential Signal from Single-Ended Source
Section, Single-Ended Source Section, Figure 26, and Table 8 15
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
7/05—Rev. 0 to Rev. A
Updated Absolute Maximum Ratings Page ...................................5
Updated Outline Dimensions ....................................................... 16
Changes to Ordering Guide .......................................................... 16
10/03—Revision 0: Initial Version
Rev. C | Page 2 of 16
Data Sheet
SPECIFICATIONS
AD8324
T
A
= 25°C, V
CC
= 3.3 V, R
L
= R
IN
= 75 Ω, V
IN
(differential) = 27.5 dBmV, unless otherwise noted. The
AD8324
is characterized using a 1:1
transformer
1
at the device output.
Table 1.
Parameter
INPUT CHARACTERISTICS
Specified AC Voltage
Input Resistance
Input Capacitance
GAIN CONTROL INTERFACE
Voltage Gain Range
Maximum Gain
Minimum Gain
Output Step Size
2
Output Step Size Temperature Coefficient
OUTPUT CHARACTERISTICS
Bandwidth (–3 dB)
Bandwidth Roll-Off
1 dB Compression Point
3
Output Noise
2
Maximum Gain
Minimum Gain
Transmit Disable
Noise Figure
2
Maximum Gain
Differential Output Impedance
OVERALL PERFORMANCE
Second-Order Harmonic Distortion
5, 3
Test Conditions/Comments
Output = 61 dBmV, maximum gain
Single-ended input
Differential input
Min
Typ
27.5
550
1100
2
58
32.5
−26.5
0.6
59
33.5
−25.5
1.0
±0.004
100
1.7
21
3.7
157
1.3
1.1
15.5
75 ± 30%
4
166
1.5
1.2
16.0
60
34.5
−24.5
1.4
Max
Unit
dBmV
Ω
Ω
pF
dB
dB
dB
dB/LSB
dB/°C
MHz
dB
dBm
dBm
nV/√Hz
nV/√Hz
nV/√Hz
dB
Ω
Gain code = 60 decimal code
Gain code = 1 decimal code
T
A
= –40°C to +85°C
All gain codes (1 decimal code to 60 decimal
codes)
f = 65 MHz
Maximum gain, f = 10 MHz, output referred
Minimum gain, f = 10 MHz, input referred
f = 10 MHz
f = 10 MHz
f = 10 MHz
f = 10 MHz
Transmit enable and transmit disable
19.6
2.1
Third-Order Harmonic Distortion (SFDR)
5, 3
Adjacent Power Channel Ratio (APCR)
2, 6
Isolation (Transmit Disable)
2
POWER CONTROL
Transmit Enable Settling Time
Transmit Disable Settling Time
Output Switching Transients
3
Output Settling
Due to Gain Change
Due to Input Step Change
f = 33 MHz, V
OUT
= 61 dBmV at maximum gain
f = 65 MHz, V
OUT
= 61 dBmV at maximum gain
f = 21 MHz, V
OUT
= 61 dBmV at maximum gain
f = 65 MHz, V
OUT
= 61 dBmV at maximum gain
Maximum gain, f = 65 MHz
Maximum gain, V
IN
= 0
Maximum gain, V
IN
= 0
Equivalent output = 31 dBmV
Equivalent output = 61 dBmV
Minimum gain to maximum gain
Maximum gain, V
IN
= 27.5 dBmV
−66
−58
−59
−54
−61
−75
2.5
3.8
2.5
27
60
30
−60
−53
−57.5
−52.5
−58
−70
dBc
dBc
dBc
dBc
dBc
dB
µs
µs
mV p-p
mV p-p
ns
ns
6
71
Rev. C | Page 3 of 16
AD8324
Parameter
POWER SUPPLY
Operating Range
Quiescent Current
Test Conditions/Comments
Min
3.13
195
25
1
−40
−25
Typ
3.3
207
39
2.5
30
Data Sheet
Max
3.47
235
50
4
500
+85
+70
Unit
V
mA
mA
mA
µA
°C
°C
Maximum gain
Minimum gain
Transmit disable (TXEN = 0)
SLEEP mode (power down)
20-lead LFCSP
20-lead QSOP
OPERATING TEMPERATURE RANGE
1
2
TOKO 458PT-1556 used for above specifications. Typical insertion loss of 0.5 dB at 10 MHz.
Guaranteed by design and characterization to ±6 sigma for T
A
= 25°C.
3
Guaranteed by design and characterization to ±3 sigma for T
A
= 25°C.
4
Measured through a 1:1 transformer.
5
Specification is worst case over all gain codes.
6
V
IN
= 27.5 dBmV, QPSK modulation, 160 kSPS symbol rate.
LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC)
DATEN, CLK, SDATA, TXEN, SLEEP, V
CC
= 3.3 V, unless otherwise noted.
Table 2.
Parameter
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current (V
INH
= 3.3 V), CLK, SDATA, DATEN
Logic 0 Current (V
INL
= 0 V), CLK, SDATA, DATEN
Logic 1 Current (V
INH
= 3.3 V), TXEN
Logic 0 Current (V
INL
= 0 V), TXEN
Logic 1 Current (V
INH
= 3.3 V), SLEEP
Logic 0 Current (V
INL
= 0 V), SLEEP
Min
2.1
0
0
−600
50
−250
50
−250
Typ
Max
3.3
0.8
20
−100
190
−30
190
−30
Unit
V
V
nA
nA
µA
µA
µA
µA
Rev. C | Page 4 of 16
Data Sheet
TIMING REQUIREMENTS
V
CC
= 3.3 V, t
R
= t
F
= 4 ns, f
CLK
= 8 MHz, unless otherwise noted.
Table 3.
Parameter
Clock Pulse Width (t
WH
)
Clock Period (t
C
)
Setup Time SDATA vs. Clock (t
DS
)
Setup Time DATEN vs. Clock (t
ES
)
Hold Time SDATA vs. Clock (t
DH
)
Hold Time DATEN vs. Clock (t
EH
)
Input Rise and Fall Times, SDATA, DATEN, Clock (t
R
, t
F
)
Min
16.0
32.0
5.0
15.0
5.0
3.0
Typ
Max
AD8324
10
Unit
ns
ns
ns
ns
ns
ns
ns
Timing Diagrams
t
DS
VALID DATA-WORD G1
MSB . . . LSB
VALID DATA-WORD G2
SDATA
t
C
t
WH
CLK
t
ES
t
EH
DATEN
8 CLOCK CYCLES
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
TXEN
t
OFF
t
GS
t
CN
04339-0-003
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
Figure 3. Serial Interface Timing
VALID DATA BIT
SDATA
MSB
MSB-1
MSB-2
t
DS
t
DH
Figure 4. SDATA Timing
Rev. C | Page 5 of 16
04339-0-004
CLK
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