Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Ambient Temperature
[2]
0
°
C to +70
°
C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
[3]
WCFS0808C1E 12ns
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
Input Load
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down
Current— TTL
Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
,
Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Com’l
Test Conditions
V
CC
= Min., I
OH
=–4.0 mA
V
CC
= Min., I
OL
=8.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
160
2.2
–0.5
–5
–5
Max.
WCFS0808C1E 15ns
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
155
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB1
I
SB2
Com’l
Max. V
CC
,
CE > V
IH
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Automatic CE
Com’l
Max. V
CC
,
Power-Down
CE > V
CC
– 0.3V
Current— CMOS V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V, f = 0
Inputs
30
30
mA
10
10
mA
]
Capacitance
[1]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
8
Unit
pF
pF
Notes:
1. V
IL
(min.) = –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. Tested initially and after any design or process changes that may affect these parameters.
Page 2 of 10
WCFS0808C1E
AC Test Loads and Waveforms
[5]
R1 481
Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
255
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
255
Ω
3.0V
10%
GND
≤
t
r
R1 481
Ω
ALL INPUT PULSES
90%
90%
10%
≤
t
r
C199–5
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT
167
Ω
1.73V
OUTPUT
Data Retention Characteristics
(
Over the Operating Range)
Parameter
V
DR
t
CDR[1]
t
R [5]
Description
V
CC
for Data Retention
Chip Deselect to Data Retention Time V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
Operation Recovery Time
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
Conditions
[6]
Min.
2.0
0
200
Max.
Unit
V
ns
µs
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Note:
5. t
R
< 3 ns for the -12 and the -15 speeds. t
R
< 5 ns for the -20 and slower speeds
6. No input may exceed V
CC
+ 0.5V.
Page 3 of 10
WCFS0808C1E
Switching Characteristics
Over the Operating Range
[3, 7]
WCFS0808C1E 12ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[8]
WCFS0808C1E 15ns
Min.
15
Max.
Unit
ns
15
3
15
7
0
7
3
7
0
15
15
10
10
0
0
9
9
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
3
ns
ns
Description
Min.
12
Max.
12
3
12
5
0
5
3
5
0
12
12
9
9
0
0
8
8
0
7
3
OE HIGH to High Z
[8, 9]
CE LOW to Low Z
[8]
CE HIGH to High Z
[8,9]
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[9]
WE HIGH to Low Z
[8]
WRITE CYCLE
[10, 11]
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels
of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
8. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
9. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
京公网安备 11010802033920号
EEWORLD
