amplifier. Fast current switches and a laser-trimmed
thin-film resistor network provide a highly accurate
and fast D/A converter.
A double-buffered latch facilitates microcomputer inter-
facing to 4-, 8-, 12-, or 16-bit data buses. The input
buffer latch holds the 12-bit data until it is transferred
to an internal 12-bit D/A converter latch, giving precise
timing control over an analog output change.
The DAC667 is specified to
±1/2LSB
maximum lin-
earity error at +25°C. The DAC667 is guaranteed
monotonic over the specification temperature range.
The DAC667 is available in 28-pin, 0.6" wide plastic
DIP package.
+V
CC
8
Ref Out
Ref In
A3
A0
A1
A2
CS
6
7
12
15
14
Power Gnd
16
Reference
–V
EE
10
1
12-Bit D/A Converter
12-Bit Parallel Latch
5k
Ω
2
5k
Ω
3
9
9.95kΩ
10V Span
Summing
Junction
V
OUT
AGND
Bipolar
Offset
20V Span
19.95k
Ω
13
11
28
4 Bits
4 Bits
4 Bits
5
4
27
•
26
•
•
25
•
•
24
•
•
23
•
•
22
•
•
21
•
•
20
•
•
19
•
•
18
•
17
DB0
LSB
DB11 •
MSB
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC667
2
ABSOLUTE MAXIMUM RATINGS
V
CC
to Power Ground .............................................................. 0V to +18V
V
EE
to Power Ground .............................................................. 0V to –18V
Digital Inputs (Pins 11–15, 17–28) to Power Ground ............. –1V to +7V
Ref In to Reference Ground ..............................................................
±12V
Bipolar Offset to Reference Ground .................................................
±12V
10V Span Resistor to Reference Ground .........................................
±12V
20V Span Resistor to Reference Ground .........................................
±24V
Ref Out, V
OUT
(Pins 6, 9) .................... Indefinite Short to Power Ground,
Momentary Short To V
CC
Power Dissipation ........................................................................ 1000mW
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
LINEARITY ERROR
max at 25
°
C
±1/2LSB
GAIN TC, max
(ppm/
°
C)
±30
PACKAGE DRAWING
NUMBER
(1)
215
PACKAGE/ORDERING INFORMATION
PRODUCT
DAC667JP
PACKAGE
28-Pin Plastic DIP
TEMPERATURE
RANGE
0°C to +70°C
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book.
TIMING SPECIFICATIONS
SYMBOL
t
DC
t
AC
t
CP
t
DH
t
SETT
PARAMETER
Data Valid to End of CS
Address Valid to End of CS
CS Pulse Width
Data Hold Time
Output Voltage Settling Time
MIN
50
100
100
0
–
TYP
–
–
–
–
2
MAX
UNITS
–
–
–
–
4
ns
ns
ns
ns
µs
All models, T
A
= +25°C, V
CC
= +12V or +15V, V
EE
= –12V or –15V.
TIMING DIAGRAMS
Write Cycle #1
Load first rank from Data Bus; A3 = 1.
t
t
AC
A3
Write Cycle #2
Load second rank from first rank; A2, A1, A0 = 1.
t
AC
A2–A0
t
DC
DB11–DB0
t
CP
CS
t
DH
Output
±1/2LSB
t
CP
CS
t
SETT
®
3
DAC667
DISCUSSION OF
SPECIFICATIONS
LINEARITY ERROR
Linearity error is defined as the deviation of the analog
output from a straight line drawn between the end points
(digital inputs all ones and all zeros). DAC667 linearity error
is specified at
±1/4LSB
max at
±1/2LSB
max for J grade.
DIFFERENTIAL LINEARITY ERROR
Differential linearity error (DLE) is the deviation from a
1LSB output change from one adjacent state to the next. A
DLE specification of 1/2LSB means that the output step size
can range from 1/2LSB to 3/2LSB when the digital input
code changes from one code word to the adjacent code word.
If the DLE is more positive than –1LSB, the D/A is said to
be monotonic.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital input values. The
DAC667 is monotonic over the specification temperature
range.
DRIFT
Gain drift is a measure of the change in the full scale range
(FSR) output over the specification temperature range. Gain
drift is expressed in parts per million per degree Celsius
(ppm/°C).
Unipolar offset drift is measured with a data input of
000
HEX
. The D/A is configured for unipolar output. Unipolar
offset drift is expressed in parts per million of full scale
range per degree Celsius (ppm of FSR/°C).
Bipolar zero drift is measured with a data input of 800
HEX
.
The D/A is configured for bipolar output. Bipolar zero drift
is expressed in parts per million of full scale range per
degree Celsius (ppm of FSR/°C).
SETTLING TIME
Settling time is the total time (including slew time) for the
output to settle to within an error band around its final value
after a change in input. Three settling times are specified to
±0.01%
of full scale range (FSR): two for FSR output
changes of 20V (10kΩ feedback) and 10V (5kΩ feedback),
and one for a 1LSB change. The 1LSB change is measured
at the major carry (7FF
HEX
to 800
HEX
, and 800
HEX
to
7FF
HEX
), the input transition at which worst-case settling
time occurs.
INTERFACE LOGIC
The bus interface logic of the DAC667 consists of four
independently addressable latches in two ranks. The first
rank consists of three four-bit input latches which can be
loaded directly from a 4-, 8-, 12- or 16-bit microprocessor/
microcontroller bus. These latches hold data temporarily
while a complete 12-bit word is assembled before loading it
into the second rank of latches. This double buffered orga-
nization prevents the generation of spurious analog output
values while the complete word is being assembled.
All latches are level-triggered. Data present when the con-
trol signals are logic 0 will enter the latch. When the control
signals return to logic 1, the data is latched. A truth table for
the control signals is presented in Table I.
CS
1
X
0
0
0
0
0
A3
X
1
1
1
1
0
0
A2
X
1
1
1
0
1
0
A1
X
1
1
0
1
1
0
A0
X
1
0
1
1
1
0
OPERATION
No Operation
No Operation
Enable Four LSBs of First Rank
Enable Four Middle Bits of First Rank
Enable Four MSBs of First Rank
Loads Second Rank from First Rank
All Latches Transparent
X = Don’t care.
TABLE I. DAC667 Truth Table.
It is permissible to enable more than one of the latches
simultaneously. If a first rank latch is enabled coincident
with the second rank latch, the data will reach the second
rank correctly if the timing specifications on page 2 are met.
LOGIC INPUT COMPATIBILITY
The DAC667 digital inputs are TTL compatible (1.4V switch-
ing level) with a low leakage, high input impedance. Thus
the inputs are suitable for being driven by any type of 5V
logic. An equivalent circuit of a digital input is shown in
Figure 1.
1kΩ
Digital Input
6.8V
DCOM
5pF
I
I
FIGURE 1. Equivalent Digital Input Circuit.
DAC667 data inputs will float to logic 1 and control inputs
will float to logic 0 if left open. It is recommended that any
unused inputs be connected to power common to improve
noise immunity.
INPUT CODING
The DAC667 accepts positive-true binary input codes.
Input coding for unipolar analog output is straight binary
(USB), where all zeros (000
HEX
) on the data inputs gives a
OPERATION
DAC667 is a monolithic integrated-circuit 12-bit D/A con-
verter. It is complete with 12-bit D/A switches and ladder
network, voltage reference, output amplifier and micro-
processor bus interface as shown in the front-page diagram.
®
DAC667
4
zero analog output and all ones (FFF
HEX
) gives an analog
output 1LSB below full scale.
Input coding for bipolar analog outputs is bipolar offset
binary (BOB), where an input code of 000
HEX
gives a minus
full-scale output, an input of FFF
HEX
gives an output 1LSB
below positive full scale, and zero occurs for an input code
of 800
HEX
.
The DAC667 can be used with two’s complement coding if
a logic inverter is used ahead of the MSB input (DB11).
INTERNAL/EXTERNAL REFERENCE USE
DAC667 contains a +10V reference which is trimmed to
typically
±0.2%
and tested and guaranteed to
±1%.
V
REF OUT
must be connected to V
REF IN
through a gain adjust resistor
with a nominal value of 50Ω. A trim potentiometer with a
nominal value of 100Ω can be used to provide adjustment to
zero gain error. If an external 10.000V reference is used, it
may be necessary to increase the trim range slightly.
The reference output may be used to drive external loads,
sourcing up to 5mA. The load current should be constant,
otherwise the gain (and bipolar offset, if connected) of the
converter will vary.
It is possible to use references other than +10V. The recom-
mended range of reference voltage is from +8V to +11V,
which allows both 8.192V and 10.24V ranges to be used.
The DAC667 is optimized for fixed-reference applications.
If the reference voltage is expected to vary over a wide
range, a CMOS multiplying D/A is a better choice.
GAIN AND OFFSET ADJUSTMENTS
Figures 2 and 3 illustrate the relationship of offset and gain
adjustments to a unipolar- and a bipolar-connected DAC667.
Offset should be adjusted first to avoid interaction of adjust-
ments.
DIGITAL
INPUT
FFF
HEX
800
HEX
7FF
HEX
000
HEX
1LSB
ANALOG OUTPUT
0 to +5V
+4.9987V
+2.5000V
+2.4987V
0.0000V
1.22mV
0 to +10V
+9.9976V
+5.0000V
+4.9976V
0.0000V
2.44mV
Analog Output
+ Full Scale
1LSB
All Bits
Logic 0
Range of
Gain Adj.
≈
±1%
Full Scale
Range
Gain Adjust
Rotates the Line
Bipolar
Offset
MSB on All
Others Off
Range of
Offset Adjust
Offset Adj.
Translates
the Line
≈
±0.4%
All Bits
Logic 1
– Full Scale
Digital Input
FIGURE 3. Relationship of Offset and Gain Adjustments for
a Bipolar D/A Converter.
Offset Adjustment
For unipolar (USB) operation, apply the digital input code
that should produce zero voltage output and adjust the offset
potentiometer for zero output. For bipolar (BOB, BTC)
operation, apply the digital input code that produces the
maximum negative output voltage and adjust the offset
potentiometer for minus full scale voltage. See Table II for
calibration values and codes.
±
2.5V
+2.4987V
0.0000V
–0.0013V
–2.5000V
1.22mV
±
5V
+4.9976V
0.0000V
–0.0024V
–5.0000V
2.44mV
±
10V
+9.9951V
0.0000V
–0.0049V
–10.0000V
4.88mV
TABLE II. Calibration Values.
+ Full Scale
1LSB
Range of
Gain Adj.
≈
±1%
Analog Output
Full Scale Range
Gain Adjust
Rotates the Line
Gain Adjustment
For either unipolar or bipolar operation, apply the digital
input that gives the maximum positive voltage output. Ad-
just the gain potentiometer for this positive full scale volt-
age. See Table II for calibration values.
Range of
Offset Adj.
≈
±0.4%
All Bits
Logic 0
All Bits
Logic 1
SETTLING TIME
PERFORMANCE
The switches, reference and output amplifier of the DAC667
are designed for optimum settling time performance (Figure
4). Figure 4a shows the full scale range step response, V
OUT
–10V to +10V to –10V, for data input 000
HEX
to FFF
HEX
to
000
HEX
. Figure 4b shows the settling time response at plus
full scale (+10V) for an output transition from –10V to
+10V. Figure 4c shows the settling time response at minus
®
Digital Input
Offset Adjust Translates the Line
FIGURE 2. Relationship of Offset and Gain Adjustments for
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