DF3D18FU
ESD Protection Diodes
Silicon Epitaxial Planar
DF3D18FU
1. Applications
•
ESD Protection
This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other
purpose, including, but not limited to, voltage regulation.
Note:
2. Features
(1)
AEC-Q101 qualified (Note 1)
Note 1: For detail information, please contact to our sales.
3. Packaging and Internal Circuit
1: Pin 1
2: Pin 2
3: GND
USM
Start of commercial production
©2017
Toshiba Electronic Devices & Storage Corporation
1
2015-05
2017-12-22
Rev.3.0
DF3D18FU
4. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
Electrostatic discharge voltage (IEC61000-4-2)(Contact)
Electrostatic discharge voltage(IEC61000-4-2)(Air)
Electrostatic discharge voltage(ISO10605)(Contact)
Electrostatic discharge voltage(ISO10605)(Air)
Peak pulse power
Peak pulse current
Junction temperature
Storage temperature
P
PK
I
PP
T
j
T
stg
(Note 3)
80
2.5
150
-55 to 150
W
A
V
ESD
(Note 2)
±30
kV
Symbol
V
ESD
Note
(Note 1)
Rating
±30
Unit
kV
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: According to IEC61000-4-2.
Note 2: According to ISO10605. (@ C = 330 pF, R = 2 kΩ)
Note 3: According to IEC61000-4-5.
Note:
©2017
Toshiba Electronic Devices & Storage Corporation
2
2017-12-22
Rev.3.0
DF3D18FU
5. Electrical Characteristics (Unless otherwise specified, T
a
= 25
)
V
RWM
: Working peak reverse
voltage
V
BR
: Reverse breakdown voltage
I
BR
: Reverse breakdown current
I
R
: Reverse current
V
C
: Clamp voltage
I
PP
: Peak pulse current
R
DYN
: Dynamic resistance
Fig. 5.1 Definitions of Electrical Characteristics
Characteristics
Working peak reverse voltage
Reverse breakdown voltage
Reverse current
Clamp voltage
Dynamic resistance
Total capacitance
Symbol
V
RWM
V
BR
I
R
V
C
R
DYN
C
t
Note
Test Condition
Min
16.2
Typ.
19
23
0.8
9
Max
12
20.5
0.1
33
10
Unit
V
V
µA
V
Ω
pF
I
BR
= 1 mA
V
RWM
= 12 V
(Note 1), (Note 3) I
PP
= 1 A
I
PP
= 2.5 A
(Note 2)
V
R
= 0 V, f = 1 MHz
Note 1: Based on IEC61000-4-5 8/20
µs
pulse.
Note 2: TLP parameter: Z0 = 50
Ω,
tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns,
extraction of dynamic resistance using a least-squares fit of TLP characteristics at I
PP
between 8 A to 16 A.
Note 3: Guaranteed by design.
©2017
Toshiba Electronic Devices & Storage Corporation
3
2017-12-22
Rev.3.0
DF3D18FU
6. Marking
7. Land Pattern Dimensions (for reference only)
(Unit: mm)
©2017
Toshiba Electronic Devices & Storage Corporation
4
2017-12-22
Rev.3.0
DF3D18FU
8. Characteristics Curves (Note)
Fig. 8.1 I - V
Fig. 8.2 I
R
- V
R
Fig. 8.3 C
t
- V
R
Note:
The above characteristics curves are presented for reference only and not guaranteed by production test,
unless otherwise noted.
©2017
Toshiba Electronic Devices & Storage Corporation
5
2017-12-22
Rev.3.0
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