DEMO MANUAL DC1620A
LTC2185, LTC2184, LTC2183,
LTC2182, LTC2181, LTC2180, LTC2188, LTC2145-14/-12,
LTC2144-14/-12, LTC2143-14/-12, LTC2142-14/-12, LTC2141-14/-12,
LTC2140-14/-12, LTC2270: 16-/14-/12-Bit,
20Msps to 125Msps Dual ADCs
DESCRIPTION
Demonstration circuit 1620A supports a family of
16-/14-/12-bit, 20Msps to 125Msps ADCs. Each assembly
features one of the following devices: LTC
®
2185, LTC2184,
LTC2183, LTC2182, LTC2181, LTC2180, LTC2188,
LTC2145-14, LTC2144-14, LTC2143-14, LTC2142-14,
LTC2141-14, LTC2140-14, LTC2145-12, LTC2144-12,
LTC2143-12, LTC2142-12, LTC2141-12, or LTC2140-12,
LTC2270 high speed, high dynamic range ADCs.
Demonstration circuit 1620A supports the LTC2185/
LTC2145 family DDR LVDS output mode.
The versions of the 1620A demo board supporting the
LTC2185 and LTC2145 series of A/D converters are listed
in Table 1. Depending on the required resolution and
sample rate, the DC1620A is supplied with the appropri-
ate ADC. The circuitry on the analog inputs is optimized
for analog input frequencies from 5MHz to 70MHz. Refer
to the data sheet for proper input networks for different
input frequencies.
Design files for this circuit board are available at
http://www.linear.com/demo
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
QuikEval and PScope are trademarks of Linear Technology Corporation. All other trademarks are
the property of their respective owners.
Table 1. DC1620 Variants
DC1620 VARIANTS
1620A-A
1620A-B
1620A-C
1620A-D
1620A-E
1620A-F
1620A-G
1620A-H
1620A-I
1620A-J
1620A-K
1620A-L
1620A-M
1620A-N
1620A-O
1620A-P
1620A-Q
1620A-R
1620A-S
1620A-T
ADC PART NUMBER
LTC2185
LTC2184
LTC2183
LTC2182
LTC2181
LTC2180
LTC2145-14
LTC2144-14
LTC2143-14
LTC2142-14
LTC2141-14
LTC2140-14
LTC2145-12
LTC2144-12
LTC2143-12
LTC2142-12
LTC2141-12
LTC2140-12
LTC2188
LTC2270
RESOLUTION
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
14-Bit
14-Bit
14-Bit
14-Bit
14-Bit
14-Bit
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
12-Bit
16-Bit
16-Bit
MAXIMUM SAMPLE RATE
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
125Msps
105Msps
80Msps
65Msps
40Msps
25Msps
20Msps
20Msps
INPUT FREQUENCY
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
5MHz to 140MHz
dc1620afb
1
DEMO MANUAL DC1620A
PERFORMANCE SUMMARY
PARAMETER
Supply Voltage—DC1620A
Analog Input Range
Logic Input Voltages
Logic Output Voltages (Differential)
Sampling Frequency (Convert Clock Frequency)
Convert Clock Level
Resolution
Input frequency range
SFDR
SNR
(T
A
= 25°C)
VALUE
6.0V Min/Max]
CONDITION
Depending on Sampling Rate and the A/D Converter Optimized for 4.5V [4.5V
Provided, This Supply Must Provide Up to 500mA
Depending on SENSE Pin Voltage
Minimum Logic High
Maximum Logic Low
Nominal Logic Levels (100Ω Load, 3.5mA Mode)
Minimum Logic Levels (100Ω Load, 3.5mA Mode)
See Table 1
Single-Ended Encode Mode (ENC– Tied to GND)
Differential Encode Mode (ENC– Not Tied to GND)
See Table 1
See Table 1
See Applicable Data Sheet
See Applicable Data Sheet
0V to 3.6V
0.2V to 3.6V
1V
P-P
to 2V
P-P
1.3V
0.6V
350mV/1.25V Common Mode
247mV/1.25V Common Mode
QUICK START PROCEDURE
Demonstration circuit 1620A is easy to set up to evaluate
the performance of the LTC2185/LTC2145 A/D converter
family. Refer to Figure 1 for proper measurement equip-
ment setup and follow the procedure below:
Setup
If a DC890 USB data acquisition and collection system
was supplied with the DC1620A demonstration circuit,
follow the DC890 Quick Start Guide to install the required
software and for connecting the DC890 to the DC1620A
and to a PC.
DC1620A Demonstration Circuit Board Jumpers
The DC1620A demonstration circuit board should have
the following jumper settings as default positions: (as
per Figure 1)
JP2-PAR/SER: Selects Parallel or Serial programming
mode. (Default: Serial)
JP3-Duty Cycle Stabilizer: Enables/Disable Duty Cycle
Stabilizer. (Default: Enable)
JP4-SHDN: Enables and disables the LTC2185/LTC2145.
(Default: Enable)
JP5-NAP: Enables and disables NAP mode (Default:
disable)
JP6-LVDS/CMOS: Selects between LVDS and CMOS output
signaling. (Default: LVDS)
Applying Power and Signals to the DC1620A
Demonstration Circuit
If a DC890 is used to acquire data from the DC1620A, the
DC890 must
first
be connected to a powered USB port
or provided an external 6V to 9V
before
applying +4.5V
to +6.0V across the pins marked V+ and GND on the
DC1620A. DC1620A requires 4.5V for proper operation.
Regulators on the board produce the voltages required for
the ADC. The DC1620A demonstration circuit requires up
to 500mA depending on the sampling rate and the A/D
converter supplied.
The DC890 data collection board is powered by the USB
cable and does require an external power supply when
collecting data from an LVDS demo board. It must be
supplied from an external 6V to 9V on turrets G7(+) and
G1(–) or the adjacent 2.1mm power jack.
dc1620afb
2
DEMO MANUAL DC1620A
QUICK START PROCEDURE
NAP
PARALLEL/SERIAL
PROGRAMMING MODE
4.5V TO 6V
–
V
+
ANALOG INPUT
CHANNEL 1
ANALOG INPUT
CHANNEL 2
PARALLEL DATA
OUTPUT TO DC890
SHDN
LVDS/CMOS
SINGLE-ENDED
ENCODE CLOCK
FROM DC1075
DUTY CYCLE
STABILIZER
Figure 1. DC1620 Setup (Zoom for Detail)
Analog Input Network
For optimal distortion and noise performance, the RC
network on the analog inputs may need to be optimized
for different analog input frequencies. For input frequen-
cies above 140MHz, refer to the respective ADC data sheet
for a proper input network. Other input networks may be
more appropriate for input frequencies less that 5MHz or
above 140MHz.
In almost all cases, filters will be required on both analog
the input and encode clock to provide data sheet SNR. In
the case of the DC1620A a bandpass filter used for the clock
should be used prior to the DC1075 clock divider board.
The filters should be located close to the inputs to avoid
reflections from impedance discontinuities at the driven
end of a long transmission line. Most filters do not present
50Ω outside the passband. In some cases, 3dB to 10dB
pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without
distortion, you may benefit from a medium power amplifier
based on a Gallium Arsenide gain block prior to the final
filter. This is particularly true at higher frequencies where
IC-based operational amplifiers may be unable to deliver
the combination of low noise figure and high IP3 point
required. A high order filter can be used prior to this final
amplifier, and a relatively lower Q filter used between the
amplifier and the demo circuit.
Encode Clock
Note: Apply an encode clock to the SMA connector on
the DC1620A demonstration circuit board marked J3.
As a default, the DC1620A is populated to have a single-
ended input.
For the best noise performance, the encode input must
be driven with a very low jitter, square wave source. The
amplitude should be large, up to 3V
P-P
or 13dBm. When
using a sinusoidal signal generator a squaring circuit can
be used. Linear Technology also provides demo board
DC1075 that divides a high frequency sine wave by four,
producing a low jitter square wave for best results with
the LTC2185/LTC2145.
dc1620afb
3
DEMO MANUAL DC1620A
QUICK START PROCEDURE
Using bandpass filters on the clock and the analog input
will improve the noise performance by reducing the
wideband noise power of the signals. In the case of the
DC1620A a bandpass filter used for the clock should be
used prior to the DC1075. Data sheet FFT plots are taken
with 10-pole LC filters made by TTE (Los Angeles, CA) to
suppress signal generator harmonics, non-harmonically
related spurs and broadband noise. Low phase noise Agilent
8644B generators are used with TTE bandpass filters for
both the clock input and the analog input.
Apply the analog input signal of interest to the SMA con-
nectors on the DC1620A demonstration circuit board
marked J5 AIN+. These inputs are capacitive coupled to
Balun transformers ETC1-1-13 (lead free part number:
MABA007159-000000).
An internally generated conversion clock output is available
on J1 which could be collected via a logic analyzer, or other
data collection system if populated with a SAMTEC MEC8-
150 type connector or collected by the DC890 QuikEval™-II
data acquisition board using PScope™ software.
Software
The DC890 is controlled by the PScope system software
provided or downloaded from the Linear Technology
website at http://www.linear.com/software/. If a DC890
was provided, follow the DC890 Quick Start Guide and
the instructions below.
To start the data collection software if “PScope.exe” is
installed (by default) in \Program Files\LTC\PScope\, double
click the PScope icon or bring up the run window under
the start menu and browse to the PScope directory and
select PScope.
If the DC1620A demonstration circuit is properly connected
to the DC890, PScope should automatically detect the
DC1620A, and configure itself accordingly. If necessary
the procedure below explains how to manually configure
PScope.
Under the Configure menu, go to ADC Configuration. Check
the Config Manually box and use the following configura-
tion options, see Figure 2:
Figure 2: ADC Configuration
Manual configuration settings:
Bits: 16
Alignment: 16
FPGA Ld: DDR LVDS
Channs: 2
Bipolar: Unchecked
Positive-Edge Clk: Checked
If everything is hooked up properly, powered, and a suitable
convert clock is present, clicking the Collect button will
result in time and frequency plots displayed in the PScope
window. Additional information and help for PScope is
available in the DC890 Quick Start Guide and in the online
help available within the PScope program itself.
Serial Programming
PScope has the ability to program the DC1620A board
serially through the DC890. There are several options
available in the LTC2185 family that are only available
through serially programming. PScope allows all of these
features to be tested.
These options are available by first clicking on the Set
Demo Bd Options icon on the PScope toolbar (Figure 3).
dc1620afb
4
DEMO MANUAL DC1620A
QUICK START PROCEDURE
• Nap – ADC core powers down while references stay
active
• Shutdown – The entire ADC is powered down
Figure 3: PScope Toolbar
Clock Inversion:
Selects the polarity of the CLKOUT signal.
• Normal (Default) – Normal CLKOUT polarity
• Inverted – CLKOUT polarity is inverted
Clock Delay:
Selects the phase delay of the CLKOUT signal.
• None (Default) – No CLKOUT delay
• 45° – CLKOUT delayed by 45°
• 90° – CLKOUT delayed by 90°
• 135° – CLKOUT delayed by 135°
Clock Duty Cycle:
Enable or disables Duty Cycle Stabilizer.
• Stabilizer off (Default) – Duty cycle stabilizer disabled
• Stabilizer on – Duty cycle stabilizer enabled
Output Current:
Selects the LVDS output drive current.
• 1.75mA (Default) - LVDS output driver current
• 2.1mA – LVDS output driver current
• 2.5mA – LVDS output driver current
• 3.0mA – LVDS output driver current
• 3.5mA – LVDS output driver current
• 4.0mA – LVDS output driver current
• 4.5mA – LVDS output driver current
Internal Termination:
Enables LVDS internal termination.
• Off (Default) – Disables internal termination
• On – Enables internal termination
Outputs:
Enables digital outputs.
• Enabled (Default) – Enables digital outputs
• Disabled – Disables digital outputs
Output Mode:
Selects digital output mode.
• Full Rate – Full rate CMOS output mode (This mode is
not supported by the DC1620A)
dc1620afb
This will bring up the menu shown in Figure 4.
Figure 4: Demobd Configuration Options
This menu allows any of the options available for the
LTC2185/LTC2145 family to be programmed serially. The
LTC2185/LTC2145 family has the following options:
Power Control:
Selects between normal operation, nap
and sleep modes.
• Normal (Default) – Entire ADC is powered, and active
• Ch1 Normal Ch2 Nap – Channel 1 remains active while
channel 2 is put into nap mode
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