BLC8G27LS-100AV
Power LDMOS transistor
Rev. 5 — 24 May 2017
Product data sheet
1. Product profile
1.1 General description
100 W LDMOS packaged asymmetrical Doherty power transistor for base station
applications at frequencies from 2496 MHz to 2690 MHz.
Table 1.
Typical performance
Typical RF performance at T
case
= 25
C in the Doherty demo board.
Test signal
1-carrier W-CDMA
[1]
f
(MHz)
2520 to 2620
V
DS
(V)
28
P
L(AV)
(W)
18
G
p
(dB)
15.5
D
(%)
45
ACPR
(dBc)
30
[1]
Test signal: 3GPP test model 1; 1 to 64 DPCH; PAR = 7.2 dB at 0.01 % probability on CCDF.
1.2 Features and benefits
Excellent ruggedness
High efficiency
Low thermal resistance providing excellent thermal stability
Decoupling leads to enable improved video bandwidth
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent pre-distortability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifier for LTE base stations and multi carrier applications in the
2496 MHz to 2690 MHz frequency range
BLC8G27LS-100AV
Power LDMOS transistor
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
[1]
Pinning
Description
drain1 (main)
drain2 (peak)
gate1 (main)
gate2 (peak)
video decoupling (main)
video decoupling (peak)
source
[1]
Simplified outline
5
1
2
6
Graphic symbol
1, 5
3
7
4
7
3
4
2, 6
aaa-007731
Connected to flange.
3. Ordering information
Table 3.
Ordering information
Package
Name
BLC8G27LS-100AV
-
Description
air cavity plastic earless flanged package; 6 leads
Version
SOT1275-1
Type number
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
T
stg
T
j
[1]
Parameter
drain-source voltage
gate-source voltage
storage temperature
junction temperature
Conditions
Min
-
0.5
65
[1]
Max
65
+13
+150
225
Unit
V
V
C
C
-
Continuous use at maximum temperature will affect the reliability, for details refer to the online MTF
calculator.
5. Thermal characteristics
Table 5.
Symbol
Thermal characteristics
Parameter
Conditions
T
case
= 80
C;
V
DS
= 28 V;
I
Dq
= 250 mA
P
L
= 18 W
P
L
= 65 W
0.314 K/W
0.289 K/W
Typ
Unit
R
th(j-case)
thermal resistance from junction to case
BLC8G27LS-100AV
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 24 May 2017
2 of 15
BLC8G27LS-100AV
Power LDMOS transistor
6. Characteristics
Table 6.
DC characteristics
T
j
= 25
C unless otherwise specified.
Symbol Parameter
Main device
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state resistance
V
GS
= 0 V; I
D
= 0.51 mA
V
DS
= 10 V; I
D
= 51 mA
V
DS
= 28 V; I
D
= 306 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 51 mA
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 1.785 A
V
GS
= 0 V; I
D
= 0.72 mA
V
DS
= 10 V; I
D
= 72 mA
V
DS
= 28 V; I
D
= 432 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 11 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 72 mA
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 2.52 A
65
1.5
1.7
-
-
-
-
-
-
1.9
2.0
-
9.6
-
294
-
2.3
2.5
1.4
-
140
451
V
V
V
A
A
nA
S
m
Conditions
Min Typ
Max Unit
0.46 -
Peak device
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state resistance
65
1.5
1.7
-
-
-
-
-
-
1.9
2.0
-
-
2.3
2.5
1.4
V
V
V
A
A
nA
S
m
13.4 -
-
210
140
323
0.62 -
Table 7.
RF characteristics
Test signal: 1-carrier W-CDMA; PAR = 7.2 dB at 0.01 % probability on the CCDF;
3GPP test model 1; 1 to 64 DPCH; f
1
= 2496 MHz; f
2
= 2690 MHz; RF performance at V
DS
= 28 V;
I
Dq
= 250 mA (main); V
GS(amp)peak
= 0.8 V; T
case
= 25
C; unless otherwise specified; in an
asymmetrical Doherty production test circuit at 2496 MHz to 2690 MHz.
Symbol
G
p
RL
in
D
ACPR
Parameter
power gain
input return loss
drain efficiency
adjacent channel power ratio
Conditions
P
L(AV)
= 17.8 W
P
L(AV)
= 17.8 W
P
L(AV)
= 17.8 W
P
L(AV)
= 17.8 W
Min
14.3
-
39
-
Typ
15.5
10
44
31
Max
-
6
-
25
Unit
dB
dB
%
dBc
Table 8.
RF characteristics
Test signal: 1-carrier W-CDMA; PAR = 7.2 dB at 0.01 % probability on the CCDF;
3GPP test model 1; 1 to 64 DPCH; f = 2690 MHz; RF performance at V
DS
= 28 V;
I
Dq
= 250 mA (main); V
GS(amp)peak
= 0.8 V; T
case
= 25
C; unless otherwise specified; in an
asymmetrical Doherty production test circuit at 2496 MHz to 2690 MHz.
Symbol Parameter
PAR
O
P
L(M)
BLC8G27LS-100AV
Conditions
Min
3.6
112
Typ
4.2
133
Max Unit
-
-
dB
W
3 of 15
output peak-to-average ratio P
L(AV)
= 50 W
peak output power
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 24 May 2017
BLC8G27LS-100AV
Power LDMOS transistor
7. Test information
7.1 Ruggedness in Doherty operation
The BLC8G27LS-100AV is capable of withstanding a load mismatch corresponding to a
VSWR = 10 : 1 through all phases under the following conditions: V
DS
= 28 V;
I
Dq
= 250 mA (main); V
GS(amp)peak
= 0.8 V; P
L
= 70 W (CW); f = 2496 MHz.
7.2 Impedance information
Table 9.
Typical impedance of main device
Measured load-pull data of main device; I
Dq
= 300 mA (main); V
DS
= 28 V.
f
(MHz)
2496
2600
2690
2496
2600
2690
[1]
[2]
Z
S
[1]
()
2.5
j6.7
3.4
j7.0
3.2
j6.2
2.5
j6.7
3.4
j7.0
3.2
j6.2
Z
L
[1]
()
4.0
j7.6
4.0
j7.6
4.0
j7.6
7.1
j5.1
6.5
j4.6
6.0
j4.1
P
L
[2]
(W)
63
61
60
47.9
44.3
40.5
D
[2]
(%)
56.0
55.6
56.1
64
63
62
G
p
[2]
(dB)
16.0
16.7
17.1
18.2
19.0
19.5
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
at 3 dB gain compression.
Table 10. Typical impedance of peak device
Measured load-pull data of peak device; I
Dq
= 400 mA (main); V
DS
= 28 V.
f
(MHz)
2496
2600
2690
2496
2600
2690
[1]
[2]
Z
S
[1]
()
2.6
j6.4
3.2
j6.9
4.3
j7.8
2.6
j6.4
3.2
j6.9
4.3
j7.8
Z
L
[1]
()
2.7
j7.1
2.1
j7.1
2.1
j7.1
4.0
j5.6
3.7
j5.1
3.3
j5.4
P
L
[2]
(W)
83
82
82
61
62
61
D
[2]
(%)
55.7
51.4
53.2
66.6
60.8
60.5
G
p
[2]
(dB)
17.8
17.7
18.4
19.7
20.1
20.6
Maximum power load
Maximum drain efficiency load
Z
S
and Z
L
defined in
Figure 1.
at 3 dB gain compression.
BLC8G27LS-100AV
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 24 May 2017
4 of 15
BLC8G27LS-100AV
Power LDMOS transistor
drain
Z
L
gate
Z
S
001aaf059
Fig 1.
Definition of transistor impedance
7.3 Recommended impedances for Doherty design
Table 11. Typical impedance of main device at 1 : 1 load
Measured load-pull data of main device; I
Dq
= 300 mA (main); V
DS
= 28 V.
f
(MHz)
2496
2600
2690
[1]
[2]
[3]
Z
S
[1]
()
2.5
j6.7
3.4
j7.0
3.2
j6.2
Z
L
[1]
()
5.1
j6.5
5.1
j6.5
5.1
j6.5
P
L
[2]
(dBm)
59
56
56
D
[3]
(%)
36.8
38.0
39.2
G
p
[3]
(dB)
20.0
20.5
21.2
Z
S
and Z
L
defined in
Figure 1.
at 3 dB gain compression.
at P
L(AV)
= 42.5 dBm.
Table 12. Typical impedance of main device at 1 : 2.5 load
Measured load-pull data of main device; I
Dq
= 300 mA (main); V
DS
= 28 V.
f
(MHz)
2496
2600
2690
[1]
[2]
[3]
Z
S
[1]
()
2.5
j6.7
3.4
j7.0
3.2
j6.2
Z
L
[1]
()
11.2
j2.7
10.0
j2.3
7.5
j0.8
P
L
[2]
(dBm)
31
30
25
D
[3]
(%)
52.0
51.1
52.2
G
p
[3]
(dB)
22.2
22.5
22.1
Z
S
and Z
L
defined in
Figure 1.
at 3 dB gain compression.
at P
L(AV)
= 42.5 dBm.
7.4 VBW in Doherty operation
The BLC8G27LS-100AV shows 130 MHz (typical) video bandwidth in Doherty demo
board in 2600 MHz at V
DS
= 28 V; I
Dq
= 250 mA and V
GS(amp)peak
= 0.8 V.
BLC8G27LS-100AV
All information provided in this document is subject to legal disclaimers.
© Ampleon Netherlands B.V. 2017. All rights reserved.
Product data sheet
Rev. 5 — 24 May 2017
5 of 15
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