LTC2923C ................................................ 0°C to 70°C
LTC2923I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MS Package ...................................................... 300°C
pacKage/orDer inForMaTion
TOP VIEW
V
CC
TOP VIEW
V
CC
ON
TRACK1
TRACK2
RAMPBUF
1
2
3
4
5
10
9
8
7
6
RAMP
GATE
FB1
FB2
GND
ON
TRACK1
TRACK2
RAMPBUF
GND
1
2
3
4
5
6
13
12 RAMP
11 GATE
10 STATUS
9
8
7
SDO
FB1
FB2
MS PACKAGE
10-LEAD PLASTIC MSOP
T
JMAX
= 125°C,
θ
JA
= 120°C/W
DE12 PACKAGE
12-LEAD (4mm
×
3mm) PLASTIC DFN
T
JMAX
= 125°C,
θ
JA
= 43°C/W
EXPOSED PAD (PIN 13)
(PCB GND CONNECTION OPTIONAL)
orDer inForMaTion
TUBE
LTC2923CMS#PBF
LTC2923IMS#PBF
LTC2923CDE#PBF
LTC2923IDE#PBF
TAPE AND REEL
LTC2923CMS#TRPBF
LTC2923IMS#TRPBF
LTC2923CDE#TRPBF
LTC2923IDE#TRPBF
http://www.linear.com/product/LTC2923#orderinfo
PART MARKING*
LTAED
LTAEE
2923
2923
PACKAGE DESCRIPTION
10-Lead Plastic MSOP
10-Lead Plastic MSOP
12-Lead Plastic DFN
12-Lead Plastic DFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/.
Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
2923fb
For more information
www.linear.com/LTC2923
LTC2923
elecTrical characTerisTics
SYMBOL
V
CC
I
CC
V
CC(UVL)
∆V
GATE
I
GATE
PARAMETER
Input Supply Range
Input Supply Current
I
FBx
= 0, I
TRACKx
= 0
I
FBx
= –1mA, I
TRACKx
= –1mA,
I
RAMPBUF
= –2mA
V
CC
Rising
I
GATE
= –1µA
Gate On, V
GATE
= 0V, No Faults
Gate Off, V
GATE
= 5V, No Faults
Gate Off, V
GATE
= 5V,
Short-Circuit Fault
V
ON
Rising
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. 2.9V < V
CC
< 5.5V unless otherwise noted (Note 3).
CONDITIONS
l
l
l
l
MIN
2.9
5
2.2
5
–7
7
5
1.212
30
0.3
160
TYP
1.3
7
2.5
25
5.5
–10
10
20
1.230
75
0.4
0
200
0
90
100
MAX
5.5
3
10
2.7
6
–13
13
50
1.248
150
0.5
±100
240
±1
150
200
30
±5
±5
0.824
0.824
±100
2
0.4
0.4
20
UNITS
V
mA
mA
V
mV
V
µA
µA
mA
V
mV
V
nA
mV
µA
mV
mV
mV
%
%
V
V
nA
V
V
V
µs
Input Supply Undervoltage Lockout
External N-Channel Gate Drive (V
GATE
– V
CC
)
GATE Pin Current
∆V
CC(UVLHYST)
Input Supply Undervoltage Lockout Hysteresis
l
l
l
l
l
l
l
V
ON(TH)
∆V
ON(HYST)
V
ON(FC)
I
ON
∆V
DS(TH)
I
RAMP
ON Pin Threshold Voltage
ON Pin Hysteresis
ON Pin Fault Clear Threshold Voltage
ON Pin Input Current
FET Drain-Source Overcurrent Voltage Threshold
(V
CC
– V
RAMP
)
RAMP Pin Input Current
V
ON
= 1.2V, V
CC
= 5.5V
l
l
0V < RAMP < V
CC
, V
CC
= 5.5V
I
RAMPBUF
= 2mA
I
RAMPBUF
= –2mA
V
RAMPBUF
= V
CC
/2, I
RAMPBUF
= 0A
I
TRACKx
= –10µA
I
TRACKx
= –1mA
I
TRACKx
= –10µA
I
TRACKx
= –1mA
V
FB
= 1.5V, V
CC
= 5.5V
1µA < I
FB
< 1mA
I
SDO
= 3mA
I
STATUS
= 3mA
V
DS
= V
CC
, V
CC
= 2.9V
l
l
l
V
RAMPBUF(OL)
RAMPBUF Low Voltage
V
RAMPBUF(OH)
RAMPBUF High Voltage (V
CC
– V
RAMPBUF
)
V
OS
I
ERROR(%)
V
TRACKx
I
FB(LEAK)
V
FB(CLAMP)
V
SDO(OL)
V
STATUS(OL)
t
PSC
Ramp Buffer Offset (V
RAMPBUF
– V
RAMP
)
I
FBx
to I
TRACKx
Current Mismatch
I
ERROR(%)
= (I
FBx
– I
TRACKx
)/I
TRACKx
TRACK Pin Voltage
I
FB
Leakage Current
V
FB
Clamp Voltage
SDO
Output Low Voltage
STATUS Output Low Voltage
Short-Circuit Propagation Delay V
DS
High
to GATE Low
–30
l
l
l
l
l
l
l
l
0
0
0
0.776
0.776
1.5
0.8
0.8
±1
1.7
0.2
0.2
10
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
The GATE pin is internally limited to a minimum of 11.5V. Driving
this pin to voltages beyond the clamp may damage the part.
Note 3:
All currents into the device pins are positive; all currents out of
device pins are negative. All voltages are referenced to ground unless
京公网安备 11010802033920号
EEWORLD
