Burr Brown Products
from Texas Instruments
DAC8550
SLAS476C – MARCH 2006 – REVISED MARCH 2006
16-BIT, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
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•
•
•
•
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Relative Accuracy: 8 LSB (Max)
Glitch Energy: 0.1 nV-s
Settling Time: 10 µs to ±0.003% FSR
Power Supply: +2.7 V to +5.5 V
16-Bit Monotonic Over Temperature
MicroPower
Operation: 200 µA at 5 V
Rail-to-Rail Output Amplifier
Power-On Reset to Midscale
Power-Down Capability
Schmitt-Triggered Digital Inputs
SYNC Interrupt Facility
2's Complement Input and Reset to Midscale
Operating Temperature Range: -40°C to 105°C
Available Packages:
– 3 mm × 5 mm MSOP-8
DESCRIPTION
The DAC8550 is a small, low-power, voltage output,
16-bit digital-to-analog converter (DAC). It is
monotonic, provides good linearity, and minimizes
undesired code to code transient voltages. The
DAC8550 uses a versatile 3-wire serial interface that
operates at clock rates of up to 30 MHz and is
compatible
with
standard
SPI™,
QSPI™,
Microwire™, and digital signal processor (DSP)
interfaces.
The DAC8550 requires an external reference voltage
to set its output range. The DAC8550 incorporates a
power-on reset circuit that ensures that the DAC
output powers up at midscale and remain there until a
valid write takes place to the device. The DAC8550
contains a power-down feature, accessed over the
serial interface, that reduces the current consumption
of the device to 200 nA at 5 V.
The low-power consumption of this device in normal
operation makes it ideal for portable battery-operated
equipment. Power consumption is 1 mW at 5 V,
reducing to 1 µW in power-down mode.
The DAC8550 is available in a MSOP-8 package.
Also see the DAC8551 binary coded counterpart of
the DAC8550.
APPLICATIONS
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•
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Process Control
Data Acquisition Systems
Closed-Loop Servo-Control
PC Peripherals
Portable Instrumentation
Programmable Attenuation
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
FB
V
REF
Ref (+)
16−Bit DAC
V
OUT
16
DAC Register
16
SYNC
SCLK
D
IN
Resistor
Networ
k
Shift Register
PWB Control
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola.
Microwire is a trademark of National Semiconductor.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
DAC8550
www.ti.com
SLAS476C – MARCH 2006 – REVISED MARCH 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
PRODUCT
RELATIVE
ACCURACY
(LSB)
±12
DIFFERENTIAL
NONLINEARITY
(LSB)
±1
PACKAGE
LEAD
MSOP-8
PACKAGE
DESIGNATOR
(1)
DGK
SPECIFICATION
TEMPERATURE
RANGE
–40°C TO 105°C
PACKAGE
MARKING
D80
DAC8550IDGKR
DAC8550IBDGKT
DAC8550B
±8
±1
MSOP-8
DGK
–40°C TO 105°C
D80
DAC8550IBDGKR
Tape and Reel, 2500
Tape and Reel, 2500
Tape and Reel, 250
ORDERING
NUMBER
DAC8550IDGKT
DAC8550
TRANSPORT
MEDIA,
QUANTITY
Tape and Reel, 250
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document or see the TI
website at
www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
UNIT
Supply voltage, V
DD
to GND
Digital input voltage range, V
I
to GND
Output voltage, V
OUT
to GND
Operating free-air temperature range, T
A
Storage temperature range, T
STG
Junction temperature range, T
J(max)
Power dissipation (DGK package)
Thermal impedance,
θ
JA
Thermal impedance,
θ
JC
(1)
–0.3 V to 6 V
–0.3 V to +V
DD
+ 0.3 V
–0.3 V to +V
DD
+ 0.3 V
–40°C to 105°C
–65°C to 150°C
150°C
(T
J
max – T
A
)/θ
JA
206°C/W
44°C/W
Stresses above those listed under
absolute maximum ratings
may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V,– 40°C to 105°C range (unless otherwise noted)
PARAMETER
STATIC PERFORMANCE
(1)
Resolution
E
L
E
D
E
O
E
FS
E
G
Relative accuracy
Differential nonlinearity
Zero-code error
Full-scale error
Gain error
Zero-code error drift
Gain temperature coefficient
PSRR
OUTPUT
V
O
Power supply rejection ratio
CHARACTERISTICS
(2)
Output voltage range
0
V
REF
V
R
L
= 2 kΩ, C
L
= 200 pF
Measured by line passing through codes -32283
and 32063.
Measured by line passing
through codes -32283 and
32063
16-bit Monotonic
DAC8550
DAC8550B
16
±5
±3
±0.25
±2
±0.05
±0.02
±5
±1
0.75
±12
±8
±1
±12
±0.5
±0.2
Bits
LSB
LSB
LSB
mV
% of FSR
% of FSR
µV/°C
ppm of
FSR/°C
mV/V
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
(2)
2
Linearity calculated using a reduced code range of -32283 to 32063; output unloaded.
Specified by design and characterization, not production tested.
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DAC8550
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SLAS476C – MARCH 2006 – REVISED MARCH 2006
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 2.7 V to 5.5 V,– 40°C to 105°C range (unless otherwise noted)
PARAMETER
t
sd
SR
Output voltage settling time
Slew rate
Capacitive load stability
Code change glitch impulse
Digital feedthrough
z
o
I
OS
t
on
DC output impedance
Short-circuit current
Power-up time
R
L
=
∞
R
L
= 2 kΩ
1 LSB change around major carry
SCLK toggling, FSYNC high
At mid-code input
V
DD
= 5 V
V
DD
= 3 V
Coming out of power-down mode V
DD
= 5 V
Coming out of power-down mode V
DD
= 3 V
TEST CONDITIONS
To ±0.003% FSR, 1200
H
to 8D00
H
, R
L
= 2 kΩ, 0
pF < C
L
< 200 pF
R
L
= 2 kΩ, C
L
= 500 pF
MIN
TYP
8
12
1.8
470
1000
0.1
0.1
1
50
20
2.5
5
95
BW = 20 kHz, V
DD
= 5 V, f
OUT
= 1 kHz
85
87
84
0
V
REF
= V
DD
= 5 V
V
REF
= V
DD
= 3.6 V
50
30
125
±1
V
DD
= 5 V
V
DD
= 3 V
V
DD
= 5 V
V
DD
= 3 V
2.4
2.1
3
2.7
Input code equals mid-scale, reference current
included, no load
V
IH
= V
DD
and V
IL
= GND
200
180
0.2
0.05
I
LOAD
= 2 mA, V
DD
= 5 V
–40
89%
105
°C
250
240
2
2
µA
5.5
0.8
0.6
V
DD
75
45
V
µA
µA
kΩ
µA
V
V
pF
V
dB
MAX
10
UNIT
µs
µs
V/µs
pF
pF
nV-s
Ω
mA
µs
AC PERFORMANCE
SNR
THD
SFDR
SINAD
V
ref
I
I(ref)
z
I(ref)
Signal-to-noise ratio (1st 19
harmonics removed)
Total harmonic distortion
Spurious-free dynamic range
Signal-to-noise and distortion
Reference voltage
Reference current input range
Reference input impedance
(3)
REFERENCE INPUT
LOGIC INPUTS
Input current
V
IL
V
IH
Low-level input voltage
High-level input voltage
Pin capacitance
POWER REQUIREMENTS
V
DD
I
DD
(normal mode)
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
I
DD
(all power-down modes)
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
POWER EFFICIENCY
I
OUT
/I
DD
TEMPERATURE RANGE
Specified performance
(3)
Specified by design and characterization, not production tested.
V
IH
= V
DD
and V
IL
= GND
µA
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DAC8550
www.ti.com
SLAS476C – MARCH 2006 – REVISED MARCH 2006
PIN CONFIGURATION
MSOP-8
(Top View)
V
DD
V
REF
V
FB
V
OUT
1
2
DAC8550
3
4
6
5
SCLK
SYNC
8
7
GND
D
IN
PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
NAME
V
DD
V
REF
V
FB
V
OUT
SYNC
SCLK
D
IN
GND
Power supply input, 2.7 V to 5.5 V.
Reference voltage input.
Feedback connection for the output amplifier.
Analog output voltage from DAC. The output amplifier has rail-to-rail operation.
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is
updated following the 24th clock (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts
as an interrupt and the write sequence is ignored by the DAC8550).
Serial clock input. Data can be transferred at rates up to 30 MHz.
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Ground reference point for all circuitry on the part.
DESCRIPTION
4
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DAC8550
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SLAS476C – MARCH 2006 – REVISED MARCH 2006
TIMING REQUIREMENTS
(1) (2)
V
DD
= 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted)
PARAMETER
t
c (3)
t
1
t
2
t
su1
t
su2
t
h
t
f
t
3
SCLK cycle time
SCLK HIGH time
SCLK LOW time
SYNC to SCLK rising edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC HIGH time
TEST CONDITIONS
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
MIN
20
20
13
13
22.5
13
0
0
5
5
4.5
4.5
0
0
50
33
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1)
(2)
(3)
All input signals are specified with t
R
= t
F
= 3 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
See
Serial Write Operation
timing diagram.
Maximum SCLK frequency is 30 MHz at V
DD
= 3.6 V to 5.5 V and 20 MHz at V
DD
= 2.7 V to 3.6 V.
SERIAL WRITE OPERATION
t
c
SCLK
t
3
t
su1
SYNC
t
h
t
su2
D
IN
DB23
DB0
t
2
t
1
t
f
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