ISL9000AIRKKZ-T datasheet, PDF

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ISL9000AIRKKZ-T: DescriptionIC REG LINEAR 2.85V/2.85V 10DFN; CategoryPower/power management The power supply circuit; File Size718KB，14 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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ISL9000AIRKKZ-T Overview

IC REG LINEAR 2.85V/2.85V 10DFN

ISL9000AIRKKZ-T Parametric

Parameter Name	Attribute value
Brand Name	Intersil
Maker	Renesas Electronics Corporation
Parts packaging code	DFN
package instruction	HVSON, SOLCC10,.11,20
Contacts	10
Reach Compliance Code	compliant
ECCN code	EAR99
Factory Lead Time	7 weeks
Is Samacsys	N
Adjustability	FIXED
Maximum drop-back voltage 1	0.325 V
Nominal dropback voltage 1	0.2 V
Maximum drop-back voltage 2	0.325 V
Maximum absolute input voltage	7.1 V
Maximum input voltage	6.5 V
Minimum input voltage	2.3 V
JESD-30 code	S-PDSO-N10
JESD-609 code	e3
length	3 mm
Humidity sensitivity level	1
Number of functions	1
Output times	2
Number of terminals	10
Working temperatureTJ-Max	125 °C
Working temperature TJ-Min	-40 °C
Maximum output current 1	0.3 A
Maximum output current 2	0.3 A
Maximum output voltage 1	2.9013 V
Minimum output voltage 1	2.7987 V
Nominal output voltage 1	2.85 V
Maximum output voltage 2	2.9013 V
Minimum output voltage 2	2.7987 V
Nominal output voltage 2	2.85 V
Package body material	PLASTIC/EPOXY
encapsulated code	HVSON
Encapsulate equivalent code	SOLCC10,.11,20
Package shape	SQUARE
Package form	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Regulator type	FIXED POSITIVE MULTIPLE OUTPUT LDO REGULATOR
Maximum seat height	1 mm
surface mount	YES
technology	CMOS
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
Maximum voltage tolerance	1.8%
width	3 mm
Base Number Matches	1

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DATASHEET

ISL9000A

Dual LDO with Low Noise, Very High PSRR and Low IQ

ISL9000A is a high performance dual LDO capable of sourcing

300mA current from each output. It has a low standby current

and very high PSRR and is stable with output capacitance of

1µF to 10µF with ESR of up to 200m.

The device integrates an individual Power-On-Reset (POR)

function for each output. The POR delay for VO2 can be

externally programmed by connecting a timing capacitor to the

CPOR pin. The POR delay for VO1 is internally fixed at

approximately 2ms. A reference bypass pin is also provided for

connecting a noise filtering capacitor for low noise and high-

PSRR applications.

The quiescent current is typically only 42µA with both LDO’s

enabled and active. Separate enable pins control each

individual LDO output. When both enable pins are low, the

device is in shutdown, typically drawing less than 0.1µA.

Several combinations of voltage outputs are standard. Output

voltage options for each LDO range from 1.5V to 3.3V. Other

output voltage options may be available upon request.

FN6391

Rev 3.00

October 15, 2015

Features

• Integrates two 300mA high performance LDOs

• Excellent transient response to large current steps

• ±1.8% accuracy over all operating conditions

• Excellent load regulation: < 0.1% voltage change across full

range of load current

• Low output noise: typically 30µV

RMS

@ 100µA (1.5V)

• Very high PSRR: 90dB @ 1kHz

• Extremely low quiescent current: 42µA (both LDOs active)

• Wide input voltage capability: 2.3V to 6.5V

• Low dropout voltage: typically 200mV @ 300mA

• Stable with 1µF to 10µF ceramic capacitors

• Separate enable and POR pins for each LDO

• Soft-start and staged turn-on to limit input current surge

during enable

• Current limit and overheat protection

• Tiny 10 Ld 3mmx3mm DFN package

• -40°C to +85°C operating temperature range

• Pb-free (RoHS compliant)

Applications

• PDAs, Cell Phones and Smart Phones

• Portable Instruments, MP3 Players

• Handheld Devices including Medical Handheld

ISL9000A

VIN (2.3 TO 6.5V)

VIN

EN1

EN2

CBYP

CPOR

VO1

VO2

POR2

POR1

GND

VO2 OK

VO2 TOO LOW

OUT1

VO1 TOO LOW

VO1

VO2

RESET2

(200ms DELAY,

C3 = 0.01µF)

RESET1

(2ms DELAY)

ENABLE1

OFF ON

ENABLE2

OFF

C1, C4, C5: 1µF X5R CERAMIC CAPACITOR

C2: 0.1µF X7R CERAMIC CAPACITOR

C3: 0.01µF X7R CERAMIC CAPACITOR

FIGURE 1. TYPICAL APPLICATION

FN6391 Rev 3.00

October 15, 2015

Page 1 of 14

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