74ALVCH16652
Rev. 3 — 12 September 2018
16-bit transceiver/register with dual enable; 3-state
Product data sheet
1. General description
The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-
type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock
inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and nSBA) or output enable
(nOEAB and nOEBA) control inputs.
Depending on the select inputs nSAB and nSBA data can directly go from input to output (real-time
mode) or data can be controlled by the clock (storage mode), when OE inputs permit this operating
mode.
The output enable inputs nOEAB and nOEBA determine the operation mode of the transceiver.
When nOEAB is LOW, no data transmission from nBn to nAn is possible and when nOEBA is
HIGH, no data transmission from nBn to nAn is possible.
When nSAB and nSBA are in the real-time transfer mode, it is also possible to store data without
using the internal D-type flip-flops by simultaneously enabling nOEAB and nOEBA. In this
configuration each output reinforces its input.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
2. Features and benefits
•
•
•
•
•
•
•
•
•
Wide supply voltage range of 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Current drive ±24 mA at V
CC
= 3.0 V.
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise and ground bounce
All data inputs have bushold
Output drive capability 50 Ω transmission lines at 85 °C
Complies with JEDEC standards:
•
JESD8-5 (2.3 V to 2.7 V)
•
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
•
HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V
•
CDM JESD22-C101E exceeds 1000 V
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74ALVCH16652DGG −40 °C to +85 °C
TSSOP56
Description
Version
plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
Nexperia
74ALVCH16652
16-bit transceiver/register with dual enable; 3-state
5.2. Pin description
Table 2. Pin description
Symbol
1A0, 1A1, 1A2, 1A3, 1A4, 1A5, 1A6, 1A7
2A0, 2A1, 2A2, 2A3, 2A4, 2A5, 2A6, 2A7
1B0, 1B1, 1B2, 1B3, 1B4, 1B5, 1B6, 1B7
2B0, 2B1, 2B2, 2B3, 2B4, 2B5, 2B6, 2B7
1OEBA, 2OEBA
1OEAB, 2OEAB
1SAB, 2SAB
1CPAB, 2CPAB
1SBA, 2SBA
1CPBA, 2CPBA
GND
V
CC
Pin
5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24
52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33
56, 29
1, 28
3, 26
2, 27
54, 31
55, 30
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
Description
data input/output
data input/output
data output/input
data output/input
output enable inputs (active-LOW)
output enable inputs (active-HIGH)
select input A-to-B
clock input A-to-B
select input B-to-A
clock input B-to-A
ground (0 V)
supply voltage
6. Functional description
Table 3. Function selection
H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition;
Operating mode
isolation, store A and B data
isolation, store A and B data
store A, hold B[1]
store A in both registers
store B, hold A[1]
store B in both registers
real-time B data to A bus
stored B data to A bus
real-time A data to B bus
stored A data to B bus
stored A data to B bus and
stored B data to A bus
[1]
Inputs
nOEAB
L
L
X
H
L
L
L
L
H
H
H
nOEBA
H
H
H
H
X
L
L
L
H
H
L
nCPAB
↑
H or L
↑
↑
H or L
↑
X
X
X
H or L
H or L
nCPBA
↑
H or L
H or L
↑
↑
↑
X
H or L
X
X
H or L
nSAB
X
X
X
L
X
X
X
X
L
H
H
nSBA
X
X
X
X
X
L
L
H
X
X
H
Data I/O
nAn
input
input
input
input
output
output
output
input
input
output
nBn
input
input
unspecified[1]
output
input
input
input
output
output
output
unspecified[1] input
The data output functions may be enabled or disabled by various signals at the nOEAB and nOEBA inputs. Data input functions are
always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs.
74ALVCH16652
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2018. All rights reserved
Product data sheet
Rev. 3 — 12 September 2018
5 / 18
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