DG611E, DG612E, DG613E
www.vishay.com
Vishay Siliconix
1.4 pC Charge Injection, 100 pA Leakage, Quad SPST Switches
DESCRIPTION
The DG611E, DG612E, and DG613E contain four
independently selectable SPST switches. They offer
improved performance over the industry standard DG611
series. The DG611E and DG612E have all switches normally
closed and normally open respectively, while the DG613E
has 2 normally open and 2 normally closed switches.
They are designed to operate from a 3 V to 12 V single
supply or from ± 3 V to ± 5 V dual supplies and are fully
specified at +3 V, +5 V and ± 5 V. All control logic inputs
have guaranteed 2 V logic high limits when operating from
+5 V or ± 5 V supplies and 1.4 V when operating from a
+3 V supply.
The DG611E, DG612E, and DG613E switches conduct
equally well in both directions and offer rail to rail analog
signal handling.
1.4 pC low charge injection, coupled with very low switch
capacitance: 3 pF, fast switching speed: t
on
/t
off
23 ns/14 ns
and excellent 3 dB bandwidth: 1 GHz, make these products
ideal for precision instrumentation, high-end data
acquisition, automated test equipment and high speed
communication applications.
Operation temperature is specified from -40 °C to +125 °C.
The DG611E, DG612E, and DG613E are available in 16 lead
SOIC, TSSOP and the space saving 1.8 mm x 2.6 mm
miniQFN packages.
FEATURES
• Low charge injection (1.4 pC typ.)
•
•
•
•
•
•
•
•
•
•
•
Leakage current < 0.25 nA at 85 °C
Low switch capacitance (C
soff
3 pF typ.)
Low R
DS(on)
- 115
max.
Fully specified with single supply operation at
3 V, 5 V, and dual supplies at ± 5 V
Low voltage, 2.5 V CMOS/TTL compatible
1 GHz, 3 dB bandwidth
Excellent isolation performance (-59 dB at 10 MHz)
Excellent crosstalk performance (-74 dB at 10 MHz)
Fully specified from -40 °C to +85 °C and -40 °C to +125 °C
16 lead SOIC, TSSOP and miniQFN package
(1.8 mm x 2.6 mm)
Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
APPLICATIONS
•
•
•
•
•
•
•
Precision instrumentation
Medical instrumentation
Automated test equipment
High speed communications applications
High-end data acquisition
Sample and hold applications
Sample and hold systems
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG611E
SOIC/TSSOP
16
DG611E
miniQFN
D
1
IN
1
IN
2
D
2
15
14
13
IN
1
D
1
S
1
V-
GND
S
4
D
4
IN
4
1
2
3
4
5
6
7
8
Top View
16
15
14
13
12
11
10
9
IN
2
D
2
S
2
V+
NC
S
3
D
3
IN
3
Pin 1
Device Marking: Txx for DG611E
(miniQFN16)
Uxx for DG612E
Vxx for DG613E
xx = Date/Lot Traceability Code
Txx
GND
S
4
3
4
S
1
V-
1
2
12
11
10
9
S
2
V+
NC
S
3
5
6
7
8
D
4
IN
4
IN
3
D
3
Top View
TRUTH TABLE
LOGIC
0
1
S17-0578-Rev. A, 24-Apr-17
DG611E
On
Off
DG612E
Off
On
Document Number: 78910
1
For technical questions, contact:
analogswitchtechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
DG611E, DG612E, DG613E
www.vishay.com
Vishay Siliconix
LIMIT
14
7
(V-) - 0.3 V to (V+) + 0.3 V
or 30 mA, whichever occurs first
30
100
-65 to +150
16-pin TSSOP
c
450
d
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25 °C, unless otherwise noted)
PARAMETER
V+ to V-
GND to V-
Digital inputs
a
, V
S
, V
D
Continuous current (any terminal)
Peak current, S or D (pulsed 1 ms, 10 % duty cycle)
Storage temperature
Power dissipation (package)
b
UNIT
V
mA
°C
mW
16-pin miniQFN
16-pin TSSOP
525
640
178
152
125
2k
1k
300
16-pin narrow SOIC
e
Thermal resistance (package)
ESD / HBM
ESD / CDM
Latch up
b
16-pin miniQFN
16-pin narrow SOIC
EIA / JESD22-A114-A
EIA / JESD22-C101-A
JESD78
°C/W
V
mA
Notes
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings
b. All leads welded or soldered to PC board
c. Derate 5.6 mW/°C above 70 °C
d. Derate 6.6 mW/°C above 70 °C
e. Derate 8 mW/°C above 70 °C
f. Manual soldering with iron is not recommended for leadless components. The miniQFN-16 is a leadless package. The end of the lead
terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper lip
cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection
S17-0578-Rev. A, 24-Apr-17
Document Number: 78910
3
For technical questions, contact:
analogswitchtechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
Microcontroller MCU
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