Advanced
Communication
Devices
Data Sheet: ACD80800
Address Resolution Logic
(8K MAC Addresses)
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Rev.1.0.0.E
Last Update: September 19, 2000
Please check ACD’s website for update
information before starting a design
Web site: http://www.acdcorp.com/tech.html
or Contact ACD at:
Email: support@acdcorp.com
Tel: 510-354-6810
Fax: 510-354-6834
ACD Confidential Material
For ACD authorized customer use only. No reproduction or redistribution without ACD’s prior permission.
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Data Sheet: ACD80800
CONTENT LIST
1. SUMMARY
2. FEATURES
3. FUNCTIONAL DESCRIPTION
4. PIN DESCRIPTION
5. INTERFACE DESCRIPTION
6. REGISTER DESCRIPTION
7. COMMAND DESCRIPTION
8. TIMING DESCRIPTION
9. ELECTRICAL SPECIFICATION
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
10. PACKAGING
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Data Sheet: ACD80800
The ACD80800 serves as an Address Resolution Logic
for ACD’s switch controller chips (ACD82124,
ACD82012 etc.) through a glueless ARL interface. It
automatically builds up an address table and can map
up to 8K MAC addresses into their associated ports.
The ACD80800 can work without a CPU in a unmanaged
switch system, or with a CPU and an ACD MIB
(ACD80900 Management Information Base). A direct
input/output interface is integrated to support a man-
agement CPU. The CPU can configure the operation
mode of the ACD80800, learn all the addresses in the
address table, add new addresses into the table, con-
trol security or filtering features of each address entry,
etc.
The ACD80800 is designed with such a high perfor-
mance that, it will never slow down the frame switching
operation conducted by the ACD’s switch controllers.
Together with the non-blocking architecture of the ACD’s
switch controllers, the chip set (a ACD switch controller
plus the ACD80800, plus ACD80900 in a managed
switch system) can provide wire speed forwarding rate
under any type of traffic load.
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Supports up to 8K MAC address lookup
Provides Glueless ARL Interface with ACD’s
switch controller chip
Provides Direct Input/Output type of interface for
the management CPU
Provides UART type of interface for the manage-
ment CPU
Wire speed address lookup time.
Wire speed address learning time.
Address can be automatically learned from switch
without THE CPU intervention
Address can be manually added by the CPU
through the CPU interface
Each MAC address can be secured by the CPU
from being changed or aged out
Each MAC address can be marked by the CPU
from receiving any frame
Each newly learned MAC address is notified to
the CPU
Each aged out MAC address is notified to the
CPU
Automatic address aging control, with
configurable aging period
0.35 micron, 3.3V CMOS technology
128-Pin PQFP package
Figure-1: ACD80800 Used in A Managed n-Port Fast Ethernet Switch System
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
P(n-1)
P(n-2)
P(n-3)
ACD82xxx
n-Port Fast Ethernet
Switch Controller
P1
P0
ACD80900
MIB
CPU
ACD80800
Address Resolution
Logic
ASRAM
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Data Sheet: ACD80800
1. SUMMARY
2. FEATURES
ACD80800 provides Address Resolution service for
ACD’s switch controller chip. ACD80800 provides a
glueless interface with ACD’s switch controller, and is
used to build an address table and provide address lookup
service to ACD’s switch controller.
Figure 2
is a block
diagram of ACD80800.
Traffic Snooping
All Ethernet frames received by ACD’s switch controller
have to be stored into memory buffer. As the frame
data are written into memory, the status of the data
shown on the data bus are displayed by ACD’s switch
controller through a state bus. ACD80800’s Switch Con-
troller Interface contains the signals of the data bus and
the state bus. By snooping the data bus and the state
bus of ACD’s switch controller, ACD80800 can detect
the occurrence of any destination MAC address and
source MAC address embedded inside each frame.
Address Learning
Each source address caught from the data bus, to-
gether with the ID of the ingress port, is passed to the
Address Learning Engine of ACD80800. The Address
Address Aging
After each source address is learned into the address
table, it has to be refreshed at least once within each
address aging period. Refresh means it is caught again
from the switch interface. If it has not occurred for a
pre-set aging period, the address aging engine will re-
move the address from the address table. After an ad-
dress is removed by the address aging engine, the CPU
will be notified through interrupt request that it needs to
read this aged out address so that it can remove this
address from the CPU’s address table.
Address Lookup
Each destination address is passed to the Address
Figure-2. ACD80800 Block Diagram
ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Switch Interface
CPU Interface
Command
Registers
Address
Registers
Address
Learning
Engine
Address
Aging
Engine
Address
Lookup
Engine
CPU Interface Engine
Address Table
(8K Entries)
Data
Registers
Control
Registers
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Data Sheet: ACD80800
3. FUNCTIONAL DESCRIPTION
Learning Engine will first determine whether the frame
is a valid frame. For a valid frame, it will first try to find
the source address from the current address table. If
that address doesn’t exist, or if it does exist but the port
ID associated with the MAC address is not the ingress
port, the address will be learned into the address table.
After an address is learned by the address learning
engine, the CPU will be notified to read this newly learned
address so that it can add it into the CPU’s address
table.
CPU Interface
ACD80800 provides a direct input/output type of inter-
face for a management CPU to access various kind of
registers inside ACD80800. The interface has 8-bit data
bus, and 5-bit address bus. The timing of read and
write operation is controlled by output enable signal and
write enable signal. For details of CPU interface timing
information, refer to the section of “Timing Descrip-
tion.”
The CPU can also choose to access the registers of
ACD80800 by sending commands to the UART data
input line. Each command is consisted by action (read
or write), register type, register index, and data. Each
result of command execution is returned to the CPU
through the UART data output line.
CPU Interface Registers
ACD80800 provides a bunch of registers for the control
CPU Interface Engine
The command sent by the control CPU is executed by
the CPU Interface Engine. For example, the CPU may
send a command to learn the first newly-learned ad-
dress. The CPU Interface Engine is responsible to find
the newly-learned address from the address table, and
passes it to CPU. The CPU may request to learn next
newly-learned address. Then, it is again the responsi-
bility of the CPU Interface Engine to search for next
newly-learned address from the address table.
Address Table
The address table can hold up to 8K MAC addresses,
together with the associated port ID, security flag, filter-
ing flag, new flag, aging information etc. The address
table resides in the embedded SRAM inside ACD80800.
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ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only.
Data Sheet: ACD80800
Lookup Engine of ACD80800. The Address Lookup
Engine checks if the destination address matches with
any existing address in the address table. If it does,
ACD80800 returns the associated Port ID to ACD’s
switch controller through the output data bus. Other-
wise, a no match result is passed to ACD’s switch con-
troller through the output data bus.
CPU. Through the registers, the CPU can read all ad-
dress entries of the address table, delete particular ad-
dresses from the table, add particular addresses into
the table, secure an address from being changed, set
filtering on some addresses, change the hashing algo-
rithm etc. Through a proper interrupt request signal, the
CPU can be notified whenever it needs to retrieve data
for a newly-learned address or an aged-out address so
that the CPU can build an exact same address table
learned by ACD80800.
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