CL-PD6833
Advance Data Sheet
FEATURES
s
Pin-compatible with the CL-PD6832
s
PC 98 v1.0 and PC 97 compliant
s
Supports the
PCI Bus Power Management
Interface for PCI to CardBus Bridges
(PCMCIA
equivalent of ACPI) including PME# support
s
High-performance support for 133-Mbyte-per-
second transfers
s
ZV (zoomed video) port support for multimedia
applications using bypass mode
s
Programmable interrupt protocol: External
Hardware, PCI/Way, PCI, or PC/PCI interrupt
signalling modes
s
Up to four multiplexed general-purpose I/O pins
s
Seven fully programmable memory or I/O
windows per socket
s
Programmable per-socket activity indicators
s
Bus master capability
s
PCI 2.1, PCI 2.2 draft, PC Card Standard (March
1997), ExCA
™,
and JEIDA 4.2 compliant
s
CL-PD672X register set compatible
s
Mixed-voltage support
s
Support for 5-V and 3.3-V PC Cards
PCI-to-CardBus Host Adapter
OVERVIEW
The CL-PD6833 easily interfaces with the 8- and 16-bit
R2 PC Cards and the 32-bit CardBus PC Cards. It is
the third device to be developed in Cirrus Logic’s family
of CardBus controllers. The CL-PD6833 gives system
designers of portable, notebook, and handheld
computers the most integrated solution for their needs.
Providing high performance, low-power consumption,
and a highly compatible and flexible interface, the
CL-PD6833 enables easy functionality for PC Card
and CardBus applications such as LANs, modems,
and multimedia applications.
The CL-PD6833 is a single-chip CardBus controller
capable of controlling two independent PC Card
and/or CardBus sockets. Featuring enhanced bus
traffic management and cycle pipelining technology,
the CL-PD6833 supports transactions at the PCI
specification limit of 133 Mbytes per second. This
significantly improves the performance over previous
Cirrus Logic controllers.
(cont.)
System Block Diagram
2)
PC
(R
s)
16 or Bu
d
ar
32
PC CARD SOCKET 1
.
......
......
......
......
......
......
......
......
......
......
.......
Ca
rd
(C
2)
PC
(R
s)
16 or Bu
d
ar
PCI
BUS
CL-PD6833
32
Ca
PC CARD SOCKET 2
.
......
......
......
......
......
......
......
......
......
......
.......
(C
rd
Version 0.3
June 1998
CL-PD6833
PCI-to-CardBus Host Adapter
OVERVIEW
(cont.)
The CL-PD6833 is compliant with the latest PC 97 and
PC 98 design guidelines. The CL-PD6833 is also
compliant with PCI 2.1, PCI 2.2 draft, PC Card
Standard (March 1997), ExCA
™
, and JEIDA 4.2
standards. Like the CL-PD6834, the register set of the
CL-PD6833 is a superset of the Intel
®
365-SL, the
CL-PD672X, and the CL-PD6832 register sets; this
ensures full compatibility with existing card and socket
services software, thus maximizing PC software
compatibility.
The CL-PD6833 is compliant with the
PCI Bus Power
Management Interface for PCI to CardBus Bridges,
which is the PCMCIA industry’s document for ACPI
compatibility. The device is also compliant with the PC
Card controller Device Class Specification.
The CL-PD6833 uses state-of-the-art clock control to
satisfy industry power consumption targets, thereby
assuring minimum power consumption during the
various operational and suspend states. The device
also offers a Hardware Suspend mode, which is a
method of powering down the host controller to the
minimum power consumption levels in addition to
ACPI-compatible power management features.
The ACPI-compatible power management features of
the CL-PD6833 plus its state-of-the-ar t clock
management and hardware suspend modes ensure
that the system designer is provided with all the power
management control needed to implement an energy-
efficient, mixed-voltage CardBus controller.
Zoomed video support had become an important con-
sideration for system designers since 1996. The
CL-PD6833 can be programmed to tristate its PC Card
interface so that graphics and audio signals from a
zoomed video–capable PC Card can be sent to the
respective graphics and audio controller zoomed video
ports. This solution is practical for multimedia applica-
tions such as DVD, full-motion video, and video confer-
encing.
The CL-PD6833 provides flexibility in non-PC
compatible applications by allowing easy translation of
PCI bus memory cycles to PC Card 16 I/O cycles for
processors with memory cycles only. In addition, the
CL-PD6833 has up to four multiplexed GPIO (general-
purpose I/O) pins to interface with external devices
that the system designer may wish to implement.
Package Outline Drawings
30.35 (1.195)
30.85 (1.215)
27.90 (1.098)
28.10 (1.106)
0.13 (0.005)
0.28 (0.011)
29.60 (1.165)
30.40 (1.197)
27.80 (1.094)
28.20 (1.110)
0.17 (0.007)
0.27 (0.011)
27.90 (1.098)
28.10 (1.106)
30.35 (1.195)
30.85 (1.215)
0.50
(0.0197)
BSC
CL-PD6833
208-PIN MQFP
25.50
(1.004)
REF
29.60 (1.165)
30.40 (1.197)
CL-PD6833
208-PIN LQFP
27.80 (1.094)
28.20 (1.110)
0.50
(0.0197)
BSC
PIN 1 INDICATOR
PIN 208
PIN 1
25.50 (1.004) REF
0.40 (0.016)
0.75 (0.030)
3.17 (0.125)
3.67 (0.144)
1.30 (0.051) REF
PIN 208
PIN 1
PIN 1 INDICATOR
0.45 (0.018)
0.75 (0.030)
1.35 (0.053)
1.45 (0.057)
1.00 (0.039) BSC
0.09 (0.004)
0.23 (0.009)
4.07
(0.160)
MAX
0.25
(0.010)
MIN
0° MIN
7° MAX
0.09 (0.004)
0.20 (0.008)
1.40 (0.055)
1.60 (0.063)
0.05 (0.002)
0.15 (0.006)
0° MIN
7° MAX
NOTES:
1) Dimensions are in millimeters (inches), and controlling dimension is millimeter.
2) The drawing above does not reflect exact package pin count.
3)
Before beginning any new design with this device, please contact Cirrus Logic for the latest package information.
CL-PD6833
PCI-to-CardBus Host Adapter
Table of Contents
1.
2.
CONVENTIONS.......................................................................................................................7
PIN INFORMATION .................................................................................................................9
2.1
2.2
2.3
Pin Diagrams........................................................................................................................................10
Pin Description Conventions ................................................................................................................12
Pin Descriptions ...................................................................................................................................13
System Architecture .............................................................................................................................25
3.1.1 PC Card Basics.......................................................................................................................25
3.1.2 CL-PD6833 R2 Windowing Capabilities..................................................................................26
3.1.3 Zoomed Video Port .................................................................................................................29
3.1.4 Interrupts .................................................................................................................................30
3.1.5 PCI/Way DMA .........................................................................................................................34
3.1.6 Power Management ................................................................................................................34
3.1.7 Socket Power Management Features .....................................................................................35
3.1.8 Bus Sizing ...............................................................................................................................37
3.1.9 Programmable PC Card Timing ..............................................................................................37
3.1.10 ATA Mode Operation ...............................................................................................................37
3.1.11 PC Card Sensing ....................................................................................................................37
Upgrading from the CL-PD6832 to the CL-PD6833.............................................................................38
3.2.1 Added Registers......................................................................................................................39
Host Access to Registers .....................................................................................................................42
Power-On Setup...................................................................................................................................44
3.
INTRODUCTION TO THE CL-PD6833..................................................................................25
3.1
3.2
3.3
3.4
4.
5.
REGISTER DESCRIPTION CONVENTIONS.......................................................................45
PCI CONFIGURATION REGISTERS....................................................................................47
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
Vendor ID and Device ID......................................................................................................................48
Command and Status ..........................................................................................................................49
Revision ID and Class Code ................................................................................................................52
Cache Line Size, Latency Timer, Header Type, and BIST ...................................................................53
Memory Base Address.........................................................................................................................54
CardBus Status ....................................................................................................................................55
PCI Bus Number, CardBus Number, Subordinate Bus Number, and CardBus Latency Timer ............57
Memory Base 0–1................................................................................................................................58
Memory Limit 0–1 ................................................................................................................................59
I/O Base 0–1 ........................................................................................................................................60
I/O Limit 0–1.........................................................................................................................................61
Interrupt Line, Interrupt Pin, and Bridge Control ..................................................................................62
Subsystem Vendor ID and Subsystem Device ID ................................................................................65
PC Card 16-Bit IF Legacy Mode Base Address...................................................................................66
Power Management Registers .............................................................................................................67
Power Management Control and Status ..............................................................................................68
DMA Slave Configuration Register.......................................................................................................70
Socket Number ....................................................................................................................................71
Configuration Miscellaneous 1 .............................................................................................................73
June 1998
ADVANCE DATA BOOK v0.3
TABLE OF CONTENTS
3
CL-PD6833
PCI-to-CardBus Host Adapter
6.
CARDBUS REGISTERS ...................................................................................................... 75
6.1
6.2
6.3
6.4
6.5
Status Event — PME_CXT .................................................................................................................. 75
Status Mask — PME_CXT................................................................................................................... 77
Present State ....................................................................................................................................... 78
Event Force .......................................................................................................................................... 80
Control — PME_CXT ........................................................................................................................... 82
Index .................................................................................................................................................... 85
Data...................................................................................................................................................... 90
Chip Revision ....................................................................................................................................... 91
Interface Status .................................................................................................................................... 92
Power Control — PME _CXT ............................................................................................................... 94
Interrupt and General Control — PME_CXT........................................................................................ 96
Card Status Change — PME_CXT ...................................................................................................... 98
Management Interrupt Configuration — PME_CXT............................................................................. 99
Mapping Enable .................................................................................................................................101
I/O Window Mapping Registers..........................................................................................................105
9.1.1 I/O Window Control ...............................................................................................................105
9.1.2 System I/O Map 0–1 Start Address Low ...............................................................................107
9.1.3 System I/O Map 0–1 Start Address High ..............................................................................107
9.1.4 System I/O Map 0–1 End Address Low ................................................................................108
9.1.5 System I/O Map 0–1 End Address High ...............................................................................108
9.1.6 Card I/O Map 0–1 Offset Address Low .................................................................................109
9.1.7 Card I/O Map 0–1 Offset Address High ................................................................................109
Memory Window Mapping Registers .................................................................................................110
9.2.1 System Memory Map 0–4 Start Address Low.......................................................................110
9.2.2 System Memory Map 0–4 Start Address High......................................................................111
9.2.3 System Memory Map 0–4 End Address Low ........................................................................112
9.2.4 System Memory Map 0–4 End Address High .......................................................................113
9.2.5 Card Memory Map 0–4 Offset Address Low .........................................................................114
9.2.6 Card Memory Map 0–4 Offset Address High ........................................................................115
7.
OPERATION REGISTERS ................................................................................................... 85
7.1
7.2
8.
DEVICE CONTROL REGISTERS........................................................................................ 91
8.1
8.2
8.3
8.4
8.5
8.6
8.7
9.
WINDOW MAPPING REGISTERS..................................................................................... 103
9.1
9.2
10. GENERAL WINDOW MAPPING REGISTERS.................................................................. 117
10.1 General Mapping Registers for I/O Mode ..........................................................................................119
10.1.1 Gen Map 0–6 Start Address Low (I/O)..................................................................................119
10.1.2 Gen Map 0–6 Start Address High (I/O).................................................................................120
10.1.3 Gen Map 0–6 End Address Low (I/O) ...................................................................................121
10.1.4 Gen Map 0–6 End Address High (I/O) ..................................................................................122
10.1.5 Gen Map 0–6 Offset Address Low (I/O)................................................................................123
10.1.6 Gen Map 0–6 Offset Address High (I/O) ...............................................................................124
10.2 General Mapping Register for Memory Mode ....................................................................................125
10.2.1 Gen Map 0–6 Start Address Low (Memory) .........................................................................125
10.2.2 Gen Map 0–6 Start Address High (Memory).........................................................................126
10.2.3 Gen Map 0–6 End Address Low (Memory)...........................................................................127
10.2.4 Gen Map 0–6 End Address High (Memory)..........................................................................128
10.2.5 Gen Map 0–6 Offset Address Low (Memory)........................................................................129
10.2.6 Gen Map 0–6 Offset Address High (Memory).......................................................................130
4
TABLE OF CONTENTS
ADVANCE DATA BOOK v0.3
June 1998
CL-PD6833
PCI-to-CardBus Host Adapter
11.
EXTENSION REGISTERS .................................................................................................131
Misc Control 1 ....................................................................................................................................132
FIFO Control ......................................................................................................................................134
Misc Control 2 ....................................................................................................................................136
Chip Information.................................................................................................................................137
ATA Control ........................................................................................................................................138
Extended Index ..................................................................................................................................140
Extended Data ...................................................................................................................................141
11.7.1 Extension Control 1...............................................................................................................142
11.7.2 Gen Map 0–6 Upper Address (Memory) ...............................................................................143
11.7.3 Pin Multiplex Control 0 Register — PME_CXT .....................................................................144
11.7.4 Pin Multiplex Control 1 Register — PME_CXT .....................................................................146
11.7.5 GPIO Output Control.............................................................................................................147
11.7.6 GPIO Input Control................................................................................................................147
11.7.7 GPIO Output Data.................................................................................................................148
11.7.8 GPIO Input Data....................................................................................................................148
11.8 Prefetch Window Register ..................................................................................................................149
11.8.1 PCI Space Control ................................................................................................................149
11.8.2 PC Card Space Control.........................................................................................................150
11.8.3 Window Type Select ..............................................................................................................150
11.8.4 Misc Control 3 .......................................................................................................................151
11.8.5 SMBus Socket Power Control Address — PME_CXT ..........................................................153
11.8.6 Gen Map 0–6 Extra Control (I/O) ..........................................................................................154
11.8.7 Gen Map 0–6 Extra Control (Memory) ..................................................................................155
11.8.8 Extension Card Status Change.............................................................................................156
11.8.9 Misc Control 4 .......................................................................................................................157
11.8.10 Misc Control 5 .......................................................................................................................158
11.8.11 Misc Control 6 .......................................................................................................................158
11.9 Device Identification and Implementation Scheme ............................................................................159
11.9.1 Mask Revision Byte...............................................................................................................159
11.9.2 Product ID Byte .....................................................................................................................160
11.9.3 Device Capability Byte A .......................................................................................................161
11.9.4 Device Capability Byte B .......................................................................................................162
11.9.5 Device Implementation Byte A ..............................................................................................163
11.9.6 Device Implementation Byte B ..............................................................................................164
11.9.7 Device Implementation Byte C ..............................................................................................165
11.9.8 Device Implementation Byte D ..............................................................................................166
11.1
11.2
11.3
11.4
11.5
11.6
11.7
12. TIMING REGISTERS...........................................................................................................167
12.1 Setup Timing 0–1 ...............................................................................................................................167
12.2 Command Timing 0–1 ........................................................................................................................168
12.3 Recovery Timing 0–1 .........................................................................................................................169
13. DMA OPERATION REGISTERS.........................................................................................171
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Low Address ......................................................................................................................................172
Mid Low Address................................................................................................................................172
Mid High Address...............................................................................................................................173
High Address......................................................................................................................................173
Low Count ..........................................................................................................................................174
Mid Count...........................................................................................................................................174
High Count .........................................................................................................................................174
June 1998
ADVANCE DATA BOOK v0.3
TABLE OF CONTENTS
5
京公网安备 11010802033920号
EEWORLD
