CL-PD6833-VC-A datasheet, PDF - EEWORLD Datasheet

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CL-PD6833-VC-A: DescriptionPCI-to-CardBus Host Adapter; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，216 Pages; ManufacturerCirrus Logic; Websitehttp://www.cirrus.com

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CL-PD6833-VC-A Overview

PCI-to-CardBus Host Adapter

CL-PD6833-VC-A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cirrus Logic
Parts packaging code	QFP
package instruction	LFQFP, QFP208,1.2SQ,20
Contacts	208
Reach Compliance Code	unknow
ECCN code	3A991.A.2
Other features	CAN ALSO OPERATE AT VCC 4.5 TO 5.5
Address bus width	32
maximum clock frequency	33 MHz
Maximum data transfer rate	133 MBps
External data bus width	32
JESD-30 code	S-PQFP-G208
JESD-609 code	e0
length	28 mm
Number of terminals	208
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP208,1.2SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	3.3/5 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	28 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCMCIA

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CL-PD6833

Advance Data Sheet

FEATURES

Pin-compatible with the CL-PD6832

PC 98 v1.0 and PC 97 compliant

Supports the

PCI Bus Power Management

Interface for PCI to CardBus Bridges

(PCMCIA

equivalent of ACPI) including PME# support

High-performance support for 133-Mbyte-per-

second transfers

ZV (zoomed video) port support for multimedia

applications using bypass mode

Programmable interrupt protocol: External

Hardware, PCI/Way, PCI, or PC/PCI interrupt

signalling modes

Up to four multiplexed general-purpose I/O pins

Seven fully programmable memory or I/O

windows per socket

Programmable per-socket activity indicators

Bus master capability

PCI 2.1, PCI 2.2 draft, PC Card Standard (March

1997), ExCA

™,

and JEIDA 4.2 compliant

CL-PD672X register set compatible

Mixed-voltage support

Support for 5-V and 3.3-V PC Cards

PCI-to-CardBus Host Adapter

OVERVIEW

The CL-PD6833 easily interfaces with the 8- and 16-bit

R2 PC Cards and the 32-bit CardBus PC Cards. It is

the third device to be developed in Cirrus Logic’s family

of CardBus controllers. The CL-PD6833 gives system

designers of portable, notebook, and handheld

computers the most integrated solution for their needs.

Providing high performance, low-power consumption,

and a highly compatible and ﬂexible interface, the

CL-PD6833 enables easy functionality for PC Card

and CardBus applications such as LANs, modems,

and multimedia applications.

The CL-PD6833 is a single-chip CardBus controller

capable of controlling two independent PC Card

and/or CardBus sockets. Featuring enhanced bus

trafﬁc management and cycle pipelining technology,

the CL-PD6833 supports transactions at the PCI

speciﬁcation limit of 133 Mbytes per second. This

signiﬁcantly improves the performance over previous

Cirrus Logic controllers.

(cont.)

System Block Diagram

16 or Bu

PC CARD SOCKET 1

......

.......

16 or Bu

PCI

BUS

CL-PD6833

PC CARD SOCKET 2

......

.......

Version 0.3

June 1998

CL-PD6833

PCI-to-CardBus Host Adapter

Table of Contents

CONVENTIONS.......................................................................................................................7

PIN INFORMATION .................................................................................................................9

2.1

2.2

2.3

Pin Diagrams........................................................................................................................................10

Pin Description Conventions ................................................................................................................12

Pin Descriptions ...................................................................................................................................13

System Architecture .............................................................................................................................25

3.1.1 PC Card Basics.......................................................................................................................25

3.1.2 CL-PD6833 R2 Windowing Capabilities..................................................................................26

3.1.3 Zoomed Video Port .................................................................................................................29

3.1.4 Interrupts .................................................................................................................................30

3.1.5 PCI/Way DMA .........................................................................................................................34

3.1.6 Power Management ................................................................................................................34

3.1.7 Socket Power Management Features .....................................................................................35

3.1.8 Bus Sizing ...............................................................................................................................37

3.1.9 Programmable PC Card Timing ..............................................................................................37

3.1.10 ATA Mode Operation ...............................................................................................................37

3.1.11 PC Card Sensing ....................................................................................................................37

Upgrading from the CL-PD6832 to the CL-PD6833.............................................................................38

3.2.1 Added Registers......................................................................................................................39

Host Access to Registers .....................................................................................................................42

Power-On Setup...................................................................................................................................44

INTRODUCTION TO THE CL-PD6833..................................................................................25

3.1

3.2

3.3

3.4

PCI CONFIGURATION REGISTERS....................................................................................47

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10

5.11

5.12

5.13

5.14

5.15

5.16

5.17

5.18

5.19

Vendor ID and Device ID......................................................................................................................48

Command and Status ..........................................................................................................................49

Revision ID and Class Code ................................................................................................................52

Cache Line Size, Latency Timer, Header Type, and BIST ...................................................................53

Memory Base Address.........................................................................................................................54

CardBus Status ....................................................................................................................................55

PCI Bus Number, CardBus Number, Subordinate Bus Number, and CardBus Latency Timer ............57

Memory Base 0–1................................................................................................................................58

Memory Limit 0–1 ................................................................................................................................59

I/O Base 0–1 ........................................................................................................................................60

I/O Limit 0–1.........................................................................................................................................61

Interrupt Line, Interrupt Pin, and Bridge Control ..................................................................................62

Subsystem Vendor ID and Subsystem Device ID ................................................................................65

PC Card 16-Bit IF Legacy Mode Base Address...................................................................................66

Power Management Registers .............................................................................................................67

Power Management Control and Status ..............................................................................................68

DMA Slave Conﬁguration Register.......................................................................................................70

Socket Number ....................................................................................................................................71

Conﬁguration Miscellaneous 1 .............................................................................................................73

June 1998

ADVANCE DATA BOOK v0.3

TABLE OF CONTENTS

CL-PD6833

PCI-to-CardBus Host Adapter

CARDBUS REGISTERS ...................................................................................................... 75

6.1

6.2

6.3

6.4

6.5

Status Event — PME_CXT .................................................................................................................. 75

Status Mask — PME_CXT................................................................................................................... 77

Present State ....................................................................................................................................... 78

Event Force .......................................................................................................................................... 80

Control — PME_CXT ........................................................................................................................... 82

Index .................................................................................................................................................... 85

Data...................................................................................................................................................... 90

Chip Revision ....................................................................................................................................... 91

Interface Status .................................................................................................................................... 92

Power Control — PME _CXT ............................................................................................................... 94

Interrupt and General Control — PME_CXT........................................................................................ 96

Card Status Change — PME_CXT ...................................................................................................... 98

Management Interrupt Conﬁguration — PME_CXT............................................................................. 99

Mapping Enable .................................................................................................................................101

I/O Window Mapping Registers..........................................................................................................105

9.1.1 I/O Window Control ...............................................................................................................105

9.1.2 System I/O Map 0–1 Start Address Low ...............................................................................107

9.1.3 System I/O Map 0–1 Start Address High ..............................................................................107

9.1.4 System I/O Map 0–1 End Address Low ................................................................................108

9.1.5 System I/O Map 0–1 End Address High ...............................................................................108

9.1.6 Card I/O Map 0–1 Offset Address Low .................................................................................109

9.1.7 Card I/O Map 0–1 Offset Address High ................................................................................109

Memory Window Mapping Registers .................................................................................................110

9.2.1 System Memory Map 0–4 Start Address Low.......................................................................110

9.2.2 System Memory Map 0–4 Start Address High......................................................................111

9.2.3 System Memory Map 0–4 End Address Low ........................................................................112

9.2.4 System Memory Map 0–4 End Address High .......................................................................113

9.2.5 Card Memory Map 0–4 Offset Address Low .........................................................................114

9.2.6 Card Memory Map 0–4 Offset Address High ........................................................................115

OPERATION REGISTERS ................................................................................................... 85

7.1

7.2

DEVICE CONTROL REGISTERS........................................................................................ 91

8.1

8.2

8.3

8.4

8.5

8.6

8.7

WINDOW MAPPING REGISTERS..................................................................................... 103

9.1

9.2

10. GENERAL WINDOW MAPPING REGISTERS.................................................................. 117

10.1 General Mapping Registers for I/O Mode ..........................................................................................119

10.1.1 Gen Map 0–6 Start Address Low (I/O)..................................................................................119

10.1.2 Gen Map 0–6 Start Address High (I/O).................................................................................120

10.1.3 Gen Map 0–6 End Address Low (I/O) ...................................................................................121

10.1.4 Gen Map 0–6 End Address High (I/O) ..................................................................................122

10.1.5 Gen Map 0–6 Offset Address Low (I/O)................................................................................123

10.1.6 Gen Map 0–6 Offset Address High (I/O) ...............................................................................124

10.2 General Mapping Register for Memory Mode ....................................................................................125

10.2.1 Gen Map 0–6 Start Address Low (Memory) .........................................................................125

10.2.2 Gen Map 0–6 Start Address High (Memory).........................................................................126

10.2.3 Gen Map 0–6 End Address Low (Memory)...........................................................................127

10.2.4 Gen Map 0–6 End Address High (Memory)..........................................................................128

10.2.5 Gen Map 0–6 Offset Address Low (Memory)........................................................................129

10.2.6 Gen Map 0–6 Offset Address High (Memory).......................................................................130

TABLE OF CONTENTS

ADVANCE DATA BOOK v0.3

June 1998

CL-PD6833

PCI-to-CardBus Host Adapter

11.

EXTENSION REGISTERS .................................................................................................131

Misc Control 1 ....................................................................................................................................132

FIFO Control ......................................................................................................................................134

Misc Control 2 ....................................................................................................................................136

Chip Information.................................................................................................................................137

ATA Control ........................................................................................................................................138

Extended Index ..................................................................................................................................140

Extended Data ...................................................................................................................................141

11.7.1 Extension Control 1...............................................................................................................142

11.7.2 Gen Map 0–6 Upper Address (Memory) ...............................................................................143

11.7.3 Pin Multiplex Control 0 Register — PME_CXT .....................................................................144

11.7.4 Pin Multiplex Control 1 Register — PME_CXT .....................................................................146

11.7.5 GPIO Output Control.............................................................................................................147

11.7.6 GPIO Input Control................................................................................................................147

11.7.7 GPIO Output Data.................................................................................................................148

11.7.8 GPIO Input Data....................................................................................................................148

11.8 Prefetch Window Register ..................................................................................................................149

11.8.1 PCI Space Control ................................................................................................................149

11.8.2 PC Card Space Control.........................................................................................................150

11.8.3 Window Type Select ..............................................................................................................150

11.8.4 Misc Control 3 .......................................................................................................................151

11.8.5 SMBus Socket Power Control Address — PME_CXT ..........................................................153

11.8.6 Gen Map 0–6 Extra Control (I/O) ..........................................................................................154

11.8.7 Gen Map 0–6 Extra Control (Memory) ..................................................................................155

11.8.8 Extension Card Status Change.............................................................................................156

11.8.9 Misc Control 4 .......................................................................................................................157

11.8.10 Misc Control 5 .......................................................................................................................158

11.8.11 Misc Control 6 .......................................................................................................................158

11.9 Device Identiﬁcation and Implementation Scheme ............................................................................159

11.9.1 Mask Revision Byte...............................................................................................................159

11.9.2 Product ID Byte .....................................................................................................................160

11.9.3 Device Capability Byte A .......................................................................................................161

11.9.4 Device Capability Byte B .......................................................................................................162

11.9.5 Device Implementation Byte A ..............................................................................................163

11.9.6 Device Implementation Byte B ..............................................................................................164

11.9.7 Device Implementation Byte C ..............................................................................................165

11.9.8 Device Implementation Byte D ..............................................................................................166

11.1

11.2

11.3

11.4

11.5

11.6

11.7

12. TIMING REGISTERS...........................................................................................................167

12.1 Setup Timing 0–1 ...............................................................................................................................167

12.2 Command Timing 0–1 ........................................................................................................................168

12.3 Recovery Timing 0–1 .........................................................................................................................169

13. DMA OPERATION REGISTERS.........................................................................................171

13.1

13.2

13.3

13.4

13.5

13.6

13.7

Low Address ......................................................................................................................................172

Mid Low Address................................................................................................................................172

Mid High Address...............................................................................................................................173

High Address......................................................................................................................................173

Low Count ..........................................................................................................................................174

Mid Count...........................................................................................................................................174

High Count .........................................................................................................................................174

June 1998

ADVANCE DATA BOOK v0.3

TABLE OF CONTENTS

CL-PD6833-VC-A Related Products

	CL-PD6833-VC-A	CL-PD6833	CL-PD6833-QC-A
Description	PCI-to-CardBus Host Adapter	PCI-to-CardBus Host Adapter	PCI-to-CardBus Host Adapter
Is it Rohs certified?	incompatible	-	incompatible
Maker	Cirrus Logic	-	Cirrus Logic
Parts packaging code	QFP	-	QFP
package instruction	LFQFP, QFP208,1.2SQ,20	-	FQFP, QFP208,1.2SQ,20
Contacts	208	-	208
Reach Compliance Code	unknow	-	unknow
ECCN code	3A991.A.2	-	3A991.A.2
Other features	CAN ALSO OPERATE AT VCC 4.5 TO 5.5	-	CAN ALSO OPERATE AT VCC 4.5 TO 5.5
Address bus width	32	-	32
maximum clock frequency	33 MHz	-	33 MHz
Maximum data transfer rate	133 MBps	-	133 MBps
External data bus width	32	-	32
JESD-30 code	S-PQFP-G208	-	S-PQFP-G208
JESD-609 code	e0	-	e0
length	28 mm	-	28 mm
Number of terminals	208	-	208
Maximum operating temperature	70 °C	-	70 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	LFQFP	-	FQFP
Encapsulate equivalent code	QFP208,1.2SQ,20	-	QFP208,1.2SQ,20
Package shape	SQUARE	-	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	-	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	240	-	NOT SPECIFIED
power supply	3.3/5 V	-	3.3/5 V
Certification status	Not Qualified	-	Not Qualified
Maximum seat height	1.6 mm	-	4.07 mm
Maximum supply voltage	3.6 V	-	3.6 V
Minimum supply voltage	3 V	-	3 V
Nominal supply voltage	3.3 V	-	3.3 V
surface mount	YES	-	YES
technology	CMOS	-	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	-	GULL WING
Terminal pitch	0.5 mm	-	0.5 mm
Terminal location	QUAD	-	QUAD
Maximum time at peak reflow temperature	30	-	NOT SPECIFIED
width	28 mm	-	28 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCMCIA	-	BUS CONTROLLER, PCMCIA

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