Features
•
Single 2.7V - 3.6V Supply
•
Dual-interface Architecture
– RapidS
™
Serial Interface: 40 MHz Maximum Clock Frequency
(SPI Modes 0 and 3 Compatible for Frequencies up to 33 MHz)
– Rapid8
™
8-bit Interface: 20 MHz Maximum Clock Frequency
Page Program Operation
– Dedicated Intelligent Programming Operation
– 16,384 Pages (1,056 Bytes/Page) Main Memory
Automated Page and Block Erase Operations
Two 1056-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming the Flash Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 10 mA Active Read Current Typical – Serial Interface
– 12 mA Active Read Current Typical – 8-bit Interface
– 5 µA CMOS Standby Current Typical
Hardware Data Protection
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
100,000 Program/Erase Cycles Per Page Typical
Data Retention – 10 Years
Commercial and Industrial Temperature Ranges
•
•
•
•
•
128-megabit
2.7-volt
Dual-interface
DataFlash
®
AT45DB1282
Preliminary
™
•
•
•
•
•
Description
The AT45DB1282 is a 2.7-volt, dual-interface sequential access Flash memory ideally
suited for a wide variety of digital voice-, image-, program code- and data-storage
Pin Configurations
Pin Name
CS
SCK/CLK
SI
SO
I/O7 - I/O0
WP
RESET
RDY/BUSY
SER/BYTE
Function
Chip Select
Serial Clock/Clock
Serial Input
Serial Output
8-bit Input/Output
Hardware Page Write
Protect Pin
Chip Reset
Ready/Busy
Serial/8-bit Interface
Control
TSOP Top View: Type 1
NC
NC
RDY/BUSY
RESET
WP
NC
NC
NC
VCC
GND
NC
NC
NC
NC
CS
SCK
SI*
SO*
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
NC
NC
NC
NC
NC
I/O7*
I/O6*
I/O5*
I/O4*
VCCP*
GNDP*
I/O3*
I/O2*
I/O1*
I/O0*
SER/BYTE*
CLK
NC
NC
NC
CBGA Top View
1
2
3
4
5
A
B
C
NC SER/BYTE NC
I/O7
VCC
I/O6
I/O5
I/O4
D
I/O2 SCK/CLK GND
E
I/O1
CS RDY/BUSY WP
SO
SI
F
I/O0
RESET I/O3
NC
NC
G
NC
GNDP VCCP
H
Note:
*Optional Use – See pin description text
for connection information.
J
Rev. 2472C–DFLSH–11/03
1
applications. This device utilizes Atmel’s e
-
STAC
™
Multi-Level Cell (MLC) memory
technology, which allows a single cell to store two bits of information delivering a
very cost effective high density Flash memory. The AT45DB1282 supports RapidS
serial interface and Rapid8 8-bit interface. RapidS serial interface is SPI compatible for
frequencies up to 33 MHz. The dual-interface allows a dedicated serial interface to be
connected to a DSP and a dedicated 8-bit interface to be connected to a microcontroller
or vice versa. However, the use of either interface is purely optional. Its 138,412,032 bits
of memory are organized as 16,384 pages of 1,056 bytes each. In addition to the 132-
megabit main memory, the AT45DB1282 also contains two SRAM buffers of 1,056
bytes each. The buffers allow the receiving of data while a page in the main Memory is
being reprogrammed, as well as writing a continuous data stream. EEPROM emulation
(bit or byte alterability) is easily handled with a self-contained three step read-modify-
write operation. Unlike conventional Flash memories that are accessed randomly with
multiple address lines and a parallel interface, the DataFlash uses either a RapidS serial
interface or a 8-bit Rapid8 interface to sequentially access its data. The simple sequen-
tial access dramatically reduces active pin count, facilitates hardware layout, increases
system reliability, minimizes switching noise, and reduces package size. The device is
optimized for use in many commercial and industrial applications where high-density,
low-pin count, low-voltage and low-power are essential. The device operates at clock
frequencies up to 40 MHz with a typical active read current consumption of 10 mA.
To allow for simple in-system reprogrammability, the AT45DB1282 does not require
high input voltages for programming. The device operates from a single power supply,
2.7V to 3.6V, for both the program and read operations. The AT45DB1282 is enabled
through the chip select pin (CS) and accessed via a three-wire interface consisting of
the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK), or an 8-bit interface
consisting of the input/output pins (I/O7 - I/O0) and the clock pin (CLK).
All programming and erase cycles are self-timed.
Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (1056 BYTES)
BUFFER 1 (1056 BYTES)
BUFFER 2 (1056 BYTES)
SCK/CLK
CS
RESET
VCC
GND
RDY/BUSY
SER/BYTE
I/O INTERFACE
SI
SO
I/O7 - I/O0
Memory Array
To provide optimal flexibility, the memory array of the AT45DB1282 is divided into three
levels of granularity comprising of sectors, blocks, and pages. The “Memory Architec-
ture Diagram” illustrates the breakdown of each level and details the number of pages
per sector and block. All program operations to the DataFlash occur on a page by page
basis. The erase operations can be performed at the block or page level.
2
AT45DB1282
2472C–DFLSH–11/03
AT45DB1282
Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0 = 8 Pages
8,448 bytes (8K + 256)
BLOCK ARCHITECTURE
SECTOR 0
BLOCK 0
BLOCK 1
PAGE ARCHITECTURE
8 Pages
PAGE 0
PAGE 1
SECTOR 1 = 248 Pages
261,888 bytes (248K + 7,936)
SECTOR 1
BLOCK 2
BLOCK 0
PAGE 6
PAGE 7
PAGE 8
BLOCK 30
SECTOR 2 = 256 Pages
270,336 bytes (256K + 8K)
BLOCK 31
SECTOR 3 = 256 Pages
270,336
bytes (256K + 8K)
SECTOR 2
BLOCK 33
BLOCK 1
BLOCK 32
PAGE 9
PAGE 14
PAGE 15
BLOCK 62
BLOCK 63
BLOCK 64
SECTOR 63 = 256 Pages
270,336 bytes (256K + 8K)
BLOCK 65
PAGE 16
PAGE 17
PAGE 18
SECTOR 64 = 256 Pages
270,336 bytes (256K + 8K)
BLOCK 2046
BLOCK 2047
PAGE 16,382
PAGE 16,383
Block = 8,448 bytes
(8K + 256)
Page = 1,056 bytes
(1K + 32)
Device Operation
The device operation is controlled by instructions from the host processor. The list of
instructions and their associated opcodes are contained in Tables 1 through 4. A valid
instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode
and the desired buffer or main memory address location. While the CS pin is low, tog-
gling the SCK/CLK pin controls the loading of the opcode and the desired buffer or main
memory address location through either the SI (serial input) pin or the 8-bit input pins
(I/O7 - I/O0). All instructions, addresses, and data are transferred with the most signifi-
cant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA10 - BFA0 to
denote the 11 address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA13 - PA0 and BA10 - BA0,
where PA13 - PA0 denotes the 14 address bits required to designate a page address
and BA10 - BA0 denotes the 11 address bits required to designate a byte address within
the page.
Read Commands
By specifying the appropriate opcode, data can be read from the main memory or from
either one of the two SRAM data buffers. The DataFlash supports RapidS and Rapid8
protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing”
diagrams in this datasheet for details on the clock cycle sequences for each mode.
CONTINUOUS ARRAY READ:
By supplying an initial starting address for the main
memory array, the Continuous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock
cycle, allowing one continuous read operation without the need of additional address
sequences. To perform a continuous read, an opcode of E8H must be clocked into the
device followed by four address bytes (which comprises 7 don’t care bits plus the 25-bit
page and byte address sequence) and a series of don’t care clock cycles (24 if using the
serial interface or 19 if using the 8-bit interface). The first 14 bits (PA13 - PA0) of the
3
2472C–DFLSH–11/03
25-bit address sequence specify which page of the main memory array to read, and the
last 11 bits (BA10 - BA0) of the 25-bit address sequence specify the starting byte
address within the page. The 24 or 19 don’t care clock cycles that follow the four
address bytes are needed to initialize the read operation. Following the don’t care clock
cycles, additional clock pulses on the SCK/CLK pin will result in data being output on
either the SO (serial output) pin or the eight output pins (I/O7- I/O0).
The CS pin must remain low during the loading of the opcode, the address bytes, the
don’t care bytes, and the reading of data. When the end of a page in main memory is
reached during a Continuous Array Read, the device will continue reading at the begin-
ning of the next page with no delays incurred during the page boundary crossover (the
crossover from the end of one page to the beginning of the next page). When the last bit
(or byte if using the 8-bit interface mode) in the main memory array has been read, the
device will continue reading back at the beginning of the first page of memory. As with
crossing over page boundaries, no delays will be incurred when wrapping around from
the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the
output pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Con-
tinuous Array Read is defined by the f
CAR
specification. The Continuous Array Read
bypasses both data buffers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ:
A main memory page read allows the user to read data
directly from any one of the 16384 pages in the main memory, bypassing both of the
data buffers and leaving the contents of the buffers unchanged. To start a page read, an
opcode of D2H must be clocked into the device followed by four address bytes (which
comprise 7 don’t care bits plus the 25-bit page and byte address sequence) and a series
of don’t care clock cycles (24 if using the serial interface or 19 if using the 8-bit inter-
face). The first 14 bits (PA13 - PA0) of the 25-bit address sequence specify the page in
main memory to be read, and the last 11 bits (BA10 - BA0) of the 25-bit address
sequence specify the starting byte address within that page. The 24 or 19 don’t care
clock cycles that follow the four address bytes are sent to initialize the read operation.
Following the don’t care bytes, additional pulses on SCK/CLK result in data being output
on either the SO (serial output) pin or the eight output pins (I/O7 - I/O0). The CS pin
must remain low during the loading of the opcode, the address bytes, the don’t care
bytes, and the reading of data. When the end of a page in main memory is reached, the
device will continue reading back at the beginning of the same page. A low-to-high tran-
sition on the CS pin will terminate the read operation and tri-state the output pins (SO or
I/O7 - I/O0). The maximum SCK/CLK frequency allowable for the Main Memory Page
Read is defined by the f
SCK
specification. The Main Memory Page Read bypasses both
data buffers and leaves the contents of the buffers unchanged.
BUFFER READ:
Data can be read from either one of the two buffers, using different
opcodes to specify which buffer to read from. With the serial interface, an opcode of
D4H is used to read data from buffer 1, and an opcode of D6H is used to read data from
buffer 2. Likewise with the 8-bit interface an opcode of 54H is used to read data from
buffer 1 and an opcode of 56H is used to read data from buffer 2. To perform a buffer
read, the opcode must be clocked into the device followed by four address bytes com-
prised of 21 don’t care bits and 11 buffer address bits (BFA10 - BFA0). Following the
four address bytes, additional don’t care bytes (one byte if using the serial interface or
two bytes if using the 8-bit interface) must be clocked in to initialize the read operation.
Since the buffer size is 1056 bytes, 11 buffer address bits are required to specify the first
byte of data to be read from the buffer. The CS pin must remain low during the loading
of the opcode, the address bytes, the don’t care bytes, and the reading of data. When
the end of a buffer is reached, the device will continue reading back at the beginning of
the buffer. A low-to-high transition on the CS pin will terminate the read operation and
tri-state the output pins (SO or I/O7 - I/O0).
4
AT45DB1282
2472C–DFLSH–11/03
AT45DB1282
Program and Erase Commands
BUFFER WRITE:
Data can be clocked in from the input pins (SI or I/O7 - I/O0) into
either buffer 1 or buffer 2. To load data into either buffer, a 1-byte opcode, 84H for buffer
1 or 87H for buffer 2, must be clocked into the device, followed by four address bytes
comprised of 21 don’t care bits and 11 buffer address bits (BFA10 - BFA0). The 11
buffer address bits specify the first byte in the buffer to be written. After the last address
byte has been clocked into the device, data can then be clocked in on subsequent clock
cycles. If the end of the data buffer is reached, the device will wrap around back to the
beginning of the buffer. Data will continue to be loaded into the buffer until a low-to-high
transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM:
A previously-erased page within main
memory can be programmed with the contents of either buffer 1 or buffer 2. The pro-
gramming time is selectable by the system through the use of different opcodes
between a normal mode and a fast mode (the fast program option will consume more
current). A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2 (98H for buffer 1 fast pro-
gram or 99H for buffer 2 fast program), must be clocked into the device followed by four
address bytes consisting of 7 don’t care bits, 14 page address bits (PA13 - PA0) that
specify the page in the main memory to be written and 11 don’t care bits. When a low-to-
high transition occurs on the CS pin, the part will program the data stored in the buffer
into the specified page in the main memory. It is necessary that the page in main mem-
ory that is being programmed has been previously erased using one of the erase
commands (Page Erase or Block Erase). The programming of the page is internally self-
timed and should take place in a maximum time of t
P
for normal programming or t
FP
for
fast programming. During this time, the status register and the RDY/BUSY pin will indi-
cate that the part is busy.
PAGE ERASE:
The Page Erase command can be used to individually erase any page
in the main memory array allowing the Buffer to Main Memory Page Program to be uti-
lized at a later time. To perform a page erase, an opcode of 81H must be loaded into the
device, followed by four address bytes comprised of 7 don’t care bits, 14 page address
bits (PA13 - PA0) that specify the page in the main memory to be erased and 11 don’t
care bits. When a low-to-high transition occurs on the CS pin, the part will erase the
selected page (the erased state is a logical 1). The erase operation is internally self-
timed and should take place in a maximum time of t
PE
. During this time, the status regis-
ter and the RDY/BUSY pin will indicate that the part is busy.
BLOCK ERASE:
A block of eight pages can be erased at one time. This command is
useful when large amounts of data has to be written into the device. This will avoid using
multiple Page Erase Commands. To perform a block erase, an opcode of 50H must be
loaded into the device, followed by four address bytes comprised of 7 don’t care bits, 11
page address bits (PA13 -PA3) and 14 don’t care bits. The 11 page address bits are
used to specify which block of eight pages is to be erased. When a low-to-high transition
occurs on the CS pin, the part will erase the selected block of eight pages. The erase
operation is internally self-timed and should take place in a maximum time of t
BE
. During
this time, the status register and the RDY/BUSY pin will indicate that the part is busy.
5
2472C–DFLSH–11/03
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