X1227
D FO R
MMENDE
O
NOT REC DESIGNS
NEW
12027
SEE IS L
DATASHEET
FN8099
Rev 2.00
May 8, 2006
2-Wire™ RTC Real TimeClock/Calendar/CPU Supervisor with EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks Time in Hours, Minutes, and Seconds
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
— Internal Feedback Resistor and Compensation
Capacitors
— 64 Position Digitally Controlled Trim Capacitor
— 6 Digital Frequency Adjustment Settings to ±30ppm
• CPU Supervisor Functions
— Power-On Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
— 64-Byte Page Write Mode
— 8 Modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
— Data Retention: 100 Years
— Endurance: 100,000 Cycles Per Byte
• 2-Wire™ Interface Interoperable with I
2
C*
— 400kHz Data Transfer Rate
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 8 Ld SOIC and 8 Ld TSSOP
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Utility Meters
HVAC Equipment
Audio/Video Components
Set Top Box/Television
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers/PDA
POS Equipment
Test Meters/Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial/Medical/Automotive
DESCRIPTION
The X1227 device is a Real Time Clock with
clock/calendar, two polled alarms with integrated 512x8
EEPROM, oscillator compensation, CPU Supervisor
(POR/LVS and WDT) and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
BLOCK DIAGRAM
OSC
Compensation
X1
X2
Frequency
Divider
1Hz
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
Battery
Switch
Circuitry
V
CC
V
BACK
32.768kHz
Oscillator
SCL
SDA
8
RESET
Watchdog
Timer
Low Voltage
Reset
Mask
Serial
Interface
Decoder
Control
Decode
Logic
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Compare
Alarm Regs
(EEPROM)
4K
EEPROM
ARRAY
FN8099 Rev 2.00
May 8, 2006
Page 1 of 28
X1227
ORDERING INFORMATION
PART NUMBER
X1227S8-4.5A
X1227S8Z-4.5A (Note 1)
X1227S8I-4.5A
X1227S8IZ-4.5A (Note 1)
X1227V8-4.5A
X1227V8Z-4.5A (Note 1)
X1227V8I-4.5A
X1227V8IZ-4.5A (Note 1)
X1227S8*
X1227S8Z* (Note 1)
X1227S8I
X1227S8IZ (Note 1)
X1227V8
X1227V8Z (Note 1)
X1227V8I
X1227V8IZ (Note 1)
X1227S8-2.7A
X1227S8Z-2.7A (Note 1)
X1227S8I-2.7A*
X1227S8IZ-2.7A* (Note 1)
X1227V8-2.7A
X1227V8Z-2.7A (Note 1)
X1227V8I-2.7A
X1227V8IZ-2.7A (Note 1)
X1227S8-2.7*
X1227S8Z-2.7 (Note 1)
X1227S8I-2.7*
X1227S8IZ-2.7 (Note 1)
X1227V8-2.7
X1227V8Z-2.7 (Note 1)
X1227V8I-2.7
X1227V8IZ-2.7 (Note 1)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For appropriate volume, any V
TRIP
value from 2.6 to 4.7V may be ordered via Intersil’s Customer Specification Program (CSPEC).
PART MARKING
X1227AL
X1227ZAL
X1227AM
X1227ZAM
1227AL
1227ALZ
1227AM
1227AMZ
X1227
X1227Z
X1227I
X1227ZI
1227
1227Z
1227I
1227IZ
X1227AN
X1227ZAN
X1227AP
X1227ZAP
1227AN
1227ANZ
1227AP
1227APZ
X1227F
X1227ZF
X1227G
X1227ZG
1227F
1227FZ
1227G
1227GZ
2.65V ± 100mV
2.7 to 5.5
2.85V ± 100mV
4.38V ± 112mV
V
CC
RANGE (V)
4.5 to 5.5
V
TRIP
4.63V ± 112mV
TEMPERATURE
RANGE (°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
8 Ld TSSOP
8 Ld TSSOP (Pb-free)
PKG. DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
M8.173
M8.173
M8.173
*Add "T1" suffix for tape and reel.
FN8099 Rev 2.00
May 8, 2006
Page 2 of 28
X1227
PIN DESCRIPTIONS
X1227
8 LD SOIC
X1
X2
RESET
V
SS
1
2
3
4
8
7
6
5
V
CC
V
BACK
SCL
SDA
X1227
8 LD TSSOP
V
BACK
V
CC
X1
X2
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
RESET
NC = No internal connection
PIN ASSIGNMENTS
Pin Number
SOIC
1
2
3
TSSOP
3
4
5
Symbol
X1
X2
RESET
Brief Description
X1.
The X1 pin is the input of an inverting amplifier and should be connected to one
pin of a 32.768kHz quartz crystal.
X2.
The X2 pin is the output of an inverting amplifier and should be connected to
one pin of a 32.768kHz quartz crystal..
Reset Output – RESET.
This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has
dropped below a fixed V
TRIP
threshold. It is an open drain active LOW output.
V
SS
.
Serial Data (SDA).
SDA is a bidirectional pin used to transfer data into and out of
the device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs.
Serial Clock (SCL).
The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not gated).
V
BACK
.
This input provides a backup supply voltage to the device. V
BACK
supplies
power to the device in the event the V
CC
supply fails. This pin can be connected to
a battery, a Supercap or tied to ground if not used.
V
CC
.
4
5
6
7
V
SS
SDA
6
7
8
1
SCL
V
BACK
8
2
V
CC
FN8099 Rev 2.00
May 8, 2006
Page 3 of 28
X1227
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65°C to +135°C
Storage Temperature ........................ -65°C to +150°C
Voltage on V
CC
, V
BACK
pin
(respect to ground)...............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above V
CC
or V
BACK
(whichever is higher)
DC Output Current .............................................. 5 mA
Lead Temperature (Soldering, 10 sec) .............. 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
DC OPERATING CHARACTERISTICS
(Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
V
CC
V
BACK
V
CB
V
BC
Parameter
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
Conditions
Min
2.7
1.8
V
BACK
-0.2
V
BACK
Typ
Max
5.5
5.5
V
BACK
-0.1
V
BACK
+0.2
Unit
V
V
V
V
Notes
OPERATING CHARACTERISTICS
Symbol
I
CC1
I
CC2
I
CC3
I
BACK
Parameter
Read Active Supply
Current
Program Supply Current
(nonvolatile)
Main Timekeeping
Current
Timekeeping Current –
(Low Voltage Sense
and Watchdog Timer
disabled
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Schmitt Trigger Input
Hysteresis
Output LOW Voltage for
SDA and RESET
Conditions
V
CC
= 2.7V
V
CC
= 5.0V
V
CC
= 2.7V
V
CC
= 5.0V
V
CC
= 2.7V
V
CC
= 5.0V
V
BACK
= 1.8V
V
BACK
= 3.3V
Min
Typ
Max
400
800
2.5
3.0
10
20
Unit
µA
µA
mA
mA
µA
µA
µA
µA
Notes
1, 5, 7, 14
2, 5, 7, 14
3, 7, 8, 14, 15
3, 6, 9, 14, 15
“See Perfor-
mance Data”
1.25
1.5
10
10
-0.5
V
CC
x 0.7 or
V
BACK
x 0.7
V
CC
x 0.2 or
V
BACK
x 0.2
V
CC
+ 0.5 or
V
BACK
+ 0.5
I
LI
I
LO
V
IL
V
IH
V
HYS
V
OL1
µA
µA
V
V
V
10
10
13
13
13
11
V
CC
related level
V
CC
= 2.7V
V
CC
= 5.5V
.05 x V
CC
or
.05 x V
BACK
0.4
0.4
V
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for t
WC
.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; t
WC
after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) V
IL
= V
CC
x 0.1, V
IH
= V
CC
x 0.9, f
SCL
= 400KHz
(6) V
CC
= 0V
(7) V
BACK
= 0V
(8) V
SDA
= V
SCL
=V
CC
, Others = GND or V
CC
FN8099 Rev 2.00
May 8, 2006
Page 4 of 28
X1227
(9) V
SDA
=V
SCL
=V
BACK
, Others = GND or V
BACK
(10)V
SDA
= GND or V
CC
, V
SCL
= GND or V
CC
, V
RESET
= GND or V
CC
(11)I
OL
= 3.0mA at 5.5V, 1.5mA at 2.7V
(12)
I
OH
= -1.0mA at 5.5V, -0.4mA at 2.7V
(13)Threshold voltages based on the higher of Vcc or Vback.
(14)Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15)Typical values are for T
A
= 25°C
Capacitance
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
OUT(1)
C
IN(1)
Parameter
Output Capacitance (SDA, RESET)
Input Capacitance (SCL)
Max.
10
10
Units
pF
pF
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Levels
Output Load
V
CC
x 0.1 to V
CC
x 0.9
10ns
V
CC
x 0.5
Standard Output Load
Figure 1. Standard Output Load for testing the device with V
CC
= 5.0V
Equivalent AC Output Load Circuit for V
CC
= 5V
5.0V
For V
OL
= 0.4V
and I
OL
= 3 mA
1533
SDA
100pF
FN8099 Rev 2.00
May 8, 2006
Page 5 of 28
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