MDT10C61
1. General Description
This ROM-Based 8-bit micro-controller uses a fully
static CMOS technology process to achieve higher
speed
and
smaller
size
with
the
low
power
u
u
LFXT－Low frequency crystal oscillator
XTAL－Standard crystal oscillator
HFXT－High frequency crystal oscillator
8-bit real time clock/counter(RTCC) with 8-bit
programmable prescaler
On-chip RC oscillator based Watchdog
Timer(WDT)
u
13 I/O pins with their own independent
direction control
consump-tion and high noise immunity. On chip
memory incl-udes 1K words of ROM, and 68 bytes of
static RAM.
2. Features
3. Applications
The followings are some of the features on the
hardware and software :
u
u
u
u
Fully CMOS static design
8-bit data bus
On chip ROM size : 1.0 K words
Internal RAM size : 81 bytes
(68 general purpose registers, 13 special
registers)
u
u
u
u
u
u
37 single word instructions
14-bit instructions
8-level stacks
Operating voltage : 2.5 V ~ 5.5 V
Operating frequency : DC ~ 20 MHz
The most fast execution time is 200 ns under
20 MHz in all single cycle instructions except
the branch instruction
u
Addressing modes include direct, indirect and
relative addressing modes
u
u
u
u
Power-on Reset
Power edge-detector Reset
Sleep Mode for power saving
3 interrupt sources:
-External INT pin
-TMR0 timer
-PortB<7:4> interrupt on change
u
4 types of oscillator can be selected by
programming option:
RC－Low cost RC oscillator
This specification are subject to be changed without notice. Any latest information please preview
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The application areas of this MDT10C61 range from
appliance motor control and high speed automotive
to low power remote transmitters/receivers, pointing
devices, and telecommunications processors, such
as Remote controller, small instruments, chargers,
toy, automobile and PC peripheral … etc.
P. 1
2005/6
Ver. 1.7
MDT10C61
4. Pin Assignment
DIP / SOP
PA2 1
18
PA3 2
17
PA4/RTCC 3
16
/MCLR 4
15
V
ss
PB0/INT
PB1
PB2
PB3
5
6
7
8
9
14
13
12
11
10
PA2
PA3
RTCC
/MCLR
VSS
VSS
PB0
PB1
PB2
PB3
1
2
3
4
5
6
7
8
9
10
SSOP
20
19
18
17
16
15
14
13
12
11
PA1
PA0
OSC1
OSC2
VDD
VDD
PB7
PB6
PB5
PB4
PA1
PA0
OSC1
OSC2
V
dd
PB7
PB6
PB5
PB4
5. Pin Function Description
Pin Name
PA0~PA3
PB0~PB7
I/O
I/O
I/O
Port A, TTL input level
Port B, TTL input level / PB0:External interrupt input ,
PB4~PB7:Interrupt on pin change
RTCC/PA4
I/O
Real Time Clock/Counter, Schmitt Trigger input levels
Open drain output
/MCLR
OSC1
OSC2
V
dd
V
ss
I
I
O
Master Clear, Schmitt Trigger input levels
Oscillator Input
Oscillator Output
Power supply
Ground
Function Description
6. Memory Map
(A) Register Map
Address
BANK0
00
01
02
03
04
Indirect Addressing Register
RTCC
PCL
STATUS
MSR
Description
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 2
2005/6
Ver. 1.7
MDT10C61
Address
05
06
0A
0B
0C~4F
BANK1
01
05
06
TMR
CPIO A
CPIO B
Port A
Port B
PCHLAT
INTS
General purpose register
Description
(1)IAR ( Indirect Address Register) : R00
(2)RTCC (Real Time Counter/Counter Register) : R01
(3) PC (Program Counter) : R02,R0A
Write PC --- from PCHLAT
LJUMP, LCALL --- from instruction word
RTWI, RET,RTFI --- from STACK
A9
A8
A7~A0
Write PC --- from ALU
LJUMP, LCALL --- from instruction word
RTWI, RET, RTFI --- from STACK
(4) STATUS (Status register) : R03
Bit
0
1
2
3
4
5
Symbol
C
HC
Z
PF
TF
RBS0
Carry bit
Half Carry bit
Zero bit
Function
Power down Flag bit
WDT Timer overflow Flag bit
Register Bank Select bit :
0 : 00H --- 7FH
1 : 80H --- FFH
7~6
——
General purpose bit
This specification are subject to be changed without notice. Any latest information please preview
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P. 3
2005/6
Ver. 1.7
MDT10C61
(5) MSR (Memory Bank Select Register) : R4
Memory Bank Select Register :
0 : 00~7F
1 : 80~FF
b7
b6
b5
b4
b3
b2
b1
b0
Indirect Addressing Mode
(6) PORT A : R05
PA4~PA0, I/O Register
(7) PORT B : R06
PB7~PB0, I/O Register
(8)PCHLAT : R0A
(9) INTS ( Interrupt Status Register ) : R0B
Bit
0
1
2
3
Symbol
RBIF
INTF
TIF
RBIE
Function
PORT B change interrupt flag. Set when PB <7:4> inputs change
Set when INT interrupt occurs. INT interrupt flag.
Set when TMR overflows.
0 : disable PB change interrupt
1 : enable PB change interrupt
4
INTS
0 : disable INT interrupt
1 : enable INT interrupt
5
TIS
0 : disable TMR interrupt
1 : enable TMR interrupt
6
7
--
GIS
Unimplemented
0 : disable global interrupt
1 : enable global interrupt
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 4
2005/6
Ver. 1.7
MDT10C61
(10) TMR (Time Mode Register) : R81
Bit
Symbol
Prescaler Value
0 0 0
0 0 1
0 1 0
0 1 1
2—0
PS2—0
1 0 0
1 0 1
1 1 0
Function
RTCC rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
WDT rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
3
PSC
4
TCE
5
TCS
6
IES
7
PBPH
1 1 1
1 : 256
1 : 128
Prescaler assignment bit :
0
—
RTCC
1
—
Watchdog Timer
RTCC signal Edge :
0
—
Increment on low-to-high transition on RTCC pin
1
—
Increment on high-to-low transition on RTCC pin
RTCC signal set :
0
—
Internal instruction cycle clock
1
—
Transition on RTCC pin
Interrupt edge select
0
—
Interrupt on falling edge on PB0
1
—
Interrupt on rising edge on PB0
PORTB pull-hi
0
—
PORTB pull-hi are enable
1
—
PORTB pull-hi are disable
(11) CPIO A (Control Port I/O Mode Register) : R85
＝“0”,
I/O pin in output mode;
＝“1”,
I/O pin in input mode.
(12) CPIO B (Control Port I/O Mode Register) : R86
＝“0”,
I/O pin in output mode;
＝“1”,
I/O pin in input mode.
(13) Configurable options for ROM:
Oscillator Type
RC
Oscillator
HFXT Oscillator
XTAL Oscillator
LFXT Oscillator
This specification are subject to be changed without notice. Any latest information please preview
http;//www.mdtic.com.tw
P. 5
2005/6
Ver. 1.7
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