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ISL78302ARBFZ-T

Description
IC REG LINEAR 1.5V/2.5V 10DFN
CategoryPower/power management    The power supply circuit   
File Size736KB,13 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
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ISL78302ARBFZ-T Overview

IC REG LINEAR 1.5V/2.5V 10DFN

ISL78302ARBFZ-T Parametric

Parameter NameAttribute value
Brand NameIntersil
MakerRenesas Electronics Corporation
Parts packaging codeDFN
package instructionSON, SOLCC10,.11,20
Contacts10
Reach Compliance Codecompliant
ECCN codeEAR99
Factory Lead Time9 weeks
Is SamacsysN
AdjustabilityFIXED
Nominal dropback voltage 10.3 V
Maximum absolute input voltage7.1 V
JESD-30 codeS-PDSO-N10
JESD-609 codee3
Humidity sensitivity level3
Output times2
Number of terminals10
Working temperatureTJ-Max125 °C
Working temperature TJ-Min-40 °C
Maximum output current 10.3 A
Nominal output voltage 12.5 V
Nominal output voltage 21.5 V
Package body materialPLASTIC/EPOXY
encapsulated codeSON
Encapsulate equivalent codeSOLCC10,.11,20
Package shapeSQUARE
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Regulator typeFIXED POSITIVE MULTIPLE OUTPUT LDO REGULATOR
Filter levelAEC-Q100
surface mountYES
technologyCMOS
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Maximum voltage tolerance1.8%
Base Number Matches1
DATASHEET
ISL78302
Dual LDO with Low Noise, High Performance and Low IQ
ISL78302 is a high performance dual LDO capable of sourcing
300mA current from each output. It has a low standby current
and is stable with an output capacitance of 1µF to 10µF and
an ESR of up to 200mΩ.
The device integrates an individual Power-On-Reset (POR)
function for each output. The POR delay for VO2 can be
externally programmed by connecting a timing capacitor to the
CPOR pin. The POR delay for VO1 is internally fixed at
approximately 2ms. A reference bypass pin is also provided for
connecting a noise filtering capacitor for low noise and high-
PSRR applications.
The quiescent current is typically only 47µA with both LDOs
enabled and active. Separate enable pins control each
individual LDO output. When both enable pins are low, the
device is in shutdown, typically drawing less than 0.5µA.
The part operates down to 2.3V and up to 6.5V input. The
typical output voltage can be as low as 1.2V and as high as
3.3V for each regulator. Please refer to the “Ordering
Information” on page 3 for standard options.
The ISL78302 is AEC-Q100 qualified at the automotive
temperature range of -40°C to +105°C.
FN7696
Rev 6.00
November 6, 2014
Features
• Integrates two 300mA high performance LDOs
• Excellent transient response to large current steps
• ±1.8% Accuracy over all operating conditions
• Excellent load regulation: <0.1% voltage change across full
range of load current
• Extremely low quiescent current: 47µA (both LDOs active)
• Wide input voltage capability: 2.3V to 6.5V
• Low dropout voltage: typically 300mV at 300mA
• Low output noise: typically 37µV
RMS
at 100µA (1.5V)
• Stable with 1µF to 10µF ceramic capacitors
• Separate enable and POR pins for each LDO
• Soft-start and staged turn-on to limit input current surge
during enable
• Current limit and over-temperature protection
• Tiny 10 Lead 3mm x 3mm DFN package
• AEC-Q100 qualified
• Pb-free (RoHS Compliant)
Applications
• Radio receivers
• Camera modules
• GPS/navigation
• Infotainment systems
ISL78302
VIN (2.3 TO 6.5V)
1
ON
2
3
4
5
C1
C2
C3
VIN
EN1
EN2
CBYP
CPOR
VO1
VO2
POR2
POR1
GND
10
9
8
7
6
C4
C5
V
OUT2
OK
V
OUT2
TOO LOW
V
OUT1
OK
V
OUT1
TOO LOW
V
OUT1
V
OUT2
RESET2
(200ms DELAY,
C3 = 0.01µF)
RESET1
(2ms DELAY)
ENABLE1
OFF ON
ENABLE2
OFF
C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.01µF X7R CERAMIC CAPACITOR
C3: 0.01µF X7R CERAMIC CAPACITOR
FIGURE 1. TYPICAL APPLICATION
FN7696 Rev 6.00
November 6, 2014
Page 1 of 13
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