®
ICL7611, ICL7612
Data Sheet
September 27, 2006
FN2919.8
1.4MHz, Low Power CMOS Operational
Amplifiers
The ICL761X series is a family of CMOS operational
amplifiers. These devices provide the designer with high
performance operation at low supply voltages and selectable
quiescent currents, and are an ideal design tool when ultra
low input current and low power dissipation are desired.
The basic amplifier will operate at supply voltages ranging
from
±1V
to
±8V,
and may be operated from a single
Lithium cell.
A unique quiescent current programming pin allows setting
of standby current to 1mA, 100μA, or 10μA, with no external
components. This results in power consumption as low as
20μW. The output swing ranges to within a few millivolts of
the supply voltages.
Of particular significance is the extremely low (1pA) input
current, input noise current of 0.01pA/√Hz, and 10
12
Ω
input
impedance. These features optimize performance in very
high source impedance applications.
The inputs are internally protected. Outputs are fully
protected against short circuits to ground or to either supply.
AC performance is excellent, with a slew rate of 1.6V/μs, and
unity gain bandwidth of 1MHz at I
Q
= 1mA.
Because of the low power dissipation, junction temperature
rise and drift are quite low. Applications utilizing these
features may include stable instruments, extended life
designs, or high density packages.
Features
• Wide Operating Voltage Range . . . . . . . . . . .
±1V
to
±8V
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 10
12
Ω
• Programmable Power Consumption . . . . . Low as 20μW
• Input Current Lower Than BIFETs . . . . . . . . . . . 1pA (Typ)
• Output Voltage Swing . . . . . . . . . . . . . . . . . . . V+ and V-
• Input Common Mode Voltage Range Greater Than Supply
Rails (ICL7612)
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Portable Instruments
• Telephone Headsets
• Hearing Aid/Microphone Amplifiers
• Meter Amplifiers
• Medical Instruments
• High Impedance Buffers
Pinouts
ICL7611, ICL7612
(PDIP, SOIC)
TOP VIEW
BAL
-IN
+IN
V-
1
2
3
4
+
8
I
Q
SET
V+
OUT
BAL
-
7
6
5
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ICL7611, ICL7612
Ordering Information
PART NUMBER
ICL7611DCBA
ICL7611DCBAZ (Note)
ICL7611DCBA-T
ICL7611DCBAZ-T (Note)
ICL7611DCPA
ICL7611DCPAZ (Note)
ICL7612BCPA
ICL7612DCBA
ICL7612DCBAZ (Note)
ICL7612DCBA-T
ICL7612DCBAZ-T (Note)
ICL7612DCPA
ICL7612DCPAZ (Note)
PART MARKING
7611DCBA
7611DCBAZ
7611DCBA
7611DCBAZ
7611DCPA
7611DCPAZ
7612BCPA
7612DCBA
7612DCBAZ
7612DCBA
7612DCBAZ
7612DCPA
7612DCPAZ
TEMP. RANGE (°C)
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel
8 Ld SOIC Tape and Reel (Pb-free)
8 Ld PDIP
8 Ld PDIP* (Pb-free)
8 Ld PDIP
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC Tape and Reel
8 Ld SOIC Tape and Reel (Pb-free)
8 Ld PDIP
8 Ld PDIP* (Pb-free)
PACKAGE
PKG. DWG. #
M8.15
M8.15
M8.15
M8.15
E8.3
E8.3
E8.3
M8.15
M8.15
M8.15
M8.15
E8.3
E8.3
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN2919.8
September 27, 2006
ICL7611, ICL7612
Absolute Maximum Ratings
Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.3 to V+ +0.3V
Differential Input Voltage (Note 1) . . . . . . . . [(V+ +0.3) - (V- -0.3)]V
Duration of Output Short Circuit (Note 2). . . . . . . . . . . . . . Unlimited
Thermal Information
Thermal Resistance (Typical, Note 3)
θ
JA
(°C/W)
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
Operating Conditions
Temperature Range
ICL761XC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Long term offset voltage stability will be degraded if large input differential voltages are applied for long periods of time.
2. The outputs may be shorted to ground or to either supply, for V
SUPPLY
≤10V.
Care must be taken to insure that the dissipation rating is not
exceeded.
3.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
Input Offset Voltage
V
SUPPLY
=
±5V,
Unless Otherwise Specified
TEST
CONDITIONS
R
S
≤
100kΩ
R
S
≤
100kΩ
ICL7612B
TEMP (°C)
+25
Full
MIN
-
-
-
-
-
-
-
-
-
-
±5.3
+5.3, -5.1
+5.3, -4.5
±4.9
±4.8
±4.9
±4.8
±4.5
±4.3
80
75
80
75
76
72
TYP
-
-
15
0.5
-
1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
104
-
102
-
83
-
MAX
5
7
-
30
300
50
400
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ICL7611D, ICL7612D
MIN
-
-
-
-
-
-
-
±4.4
±4.2
±3.7
±5.3
+5.3, -5.1
+5.3, -4.5
±4.9
±4.8
±4.9
±4.8
±4.5
±4.3
80
75
80
75
76
72
TYP
-
-
25
0.5
-
1.0
-
-
-
-
-
-
-
-
-
-
-
-
-
104
-
102
-
83
-
MAX
15
20
-
30
300
50
400
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UNITS
mV
mV
μV/°C
pA
pA
pA
pA
V
V
V
V
V
V
V
V
V
V
V
V
dB
dB
dB
dB
dB
dB
SYMBOL
V
OS
ΔV
OS
/ΔT
I
OS
Temperature
Coefficient of V
OS
Input Offset Current
-
+25
Full
Input Bias Current
I
BIAS
+25
Full
Common Mode
Voltage Range
(ICL7611 Only)
Extended Common
Mode Voltage Range
(ICL7612 Only)
Output Voltage Swing
V
CMR
I
Q
= 10μA
I
Q
= 100μA
I
Q
= 1mA
+25
+25
+25
+25
+25
+25
+25
Full
V
CMR
I
Q
= 10μA
I
Q
= 100μA
I
Q
= 1mA
V
OUT
I
Q
= 10μA, R
L
= 1MΩ
I
Q
= 100μA, R
L
= 100kΩ
+25
Full
I
Q
= 1mA, R
L
= 10kΩ
V
O
=
±4.0V,
R
L
= 1MΩ,
I
Q
= 10μA
V
O
=
±4.0V,
R
L
= 100kΩ,
I
Q
= 100μA
V
O
=
±4.0V,
R
L
= 10kΩ,
I
Q
= 1mA
+25
Full
Large Signal Voltage
Gain
A
VOL
+25
Full
+25
Full
+25
Full
3
FN2919.8
September 27, 2006
ICL7611, ICL7612
Electrical Specifications
PARAMETER
Unity Gain Bandwidth
V
SUPPLY
=
±5V,
Unless Otherwise Specified
(Continued)
TEST
CONDITIONS
I
Q
= 10μA
I
Q
= 100μA
I
Q
= 1mA
Input Resistance
Common Mode
Rejection Ratio
R
IN
CMRR
R
S
≤
100kΩ, I
Q
= 10μA
R
S
≤
100kΩ, I
Q
= 100μA
R
S
≤
100kΩ, I
Q
= 1mA
Power Supply
Rejection Ratio
(V
SUPPLY
=
±8V
to
±2V)
Input Referred Noise
Voltage
Input Referred Noise
Current
Supply Current
(No Signal, No Load)
PSRR
R
S
≤
100kΩ, I
Q
= 10μA
R
S
≤
100kΩ, I
Q
= 100μA
R
S
≤
100kΩ, I
Q
= 1mA
e
N
i
N
I
SUPPLY
R
S
= 100Ω, f = 1kHz
R
S
= 100Ω, f = 1kHz
I
Q
SET = +5V, Low Bias
I
Q
SET = 0V,
Medium Bias
I
Q
SET = -5V, High Bias
Channel Separation
Slew Rate
(A
V
= 1, C
L
= 100pF,
V
IN
= 8V
P-P
)
Rise Time
(V
IN
= 50mV,
C
L
= 100pF)
Overshoot Factor
(V
IN
= 50mV,
C
L
= 100pF)
V
O1
/V
O2
SR
A
V
= 100
I
Q
= 10μA, R
L
= 1MΩ
I
Q
= 100μA, R
L
= 100kΩ
I
Q
= 1mA, R
L
= 10kΩ
t
r
I
Q
= 10μA, R
L
= 1MΩ
I
Q
= 100μA, R
L
= 100kΩ
I
Q
= 1mA, R
L
= 10kΩ
OS
I
Q
= 10μA, R
L
= 1MΩ
I
Q
= 100μA, R
L
= 100kΩ
I
Q
= 1mA, R
L
= 10kΩ
ICL7612B
TEMP (°C)
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
MIN
-
-
-
-
70
70
60
80
80
70
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
0.044
0.48
1.4
10
12
96
91
87
94
86
77
100
0.01
0.01
0.1
1.0
120
0.016
0.16
1.6
20
2
0.9
5
10
40
MAX
-
-
-
-
-
-
-
-
-
-
-
-
0.02
0.25
2.5
-
-
-
-
-
-
-
-
-
-
ICL7611D, ICL7612D
MIN
-
-
-
-
70
70
60
80
80
70
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
0.044
0.48
1.4
10
12
96
91
87
94
86
77
100
0.01
0.01
0.1
1.0
120
0.016
0.16
1.6
20
2
0.9
5
10
40
MAX
-
-
-
-
-
-
-
-
-
-
-
-
0.02
0.25
2.5
-
-
-
-
-
-
-
-
-
-
UNITS
MHz
MHz
MHz
Ω
dB
dB
dB
dB
dB
dB
nV/√Hz
pA/√Hz
mA
mA
mA
dB
V/μs
V/μs
V/μs
μs
μs
μs
%
%
%
SYMBOL
GBW
Electrical Specifications
PARAMETER
Input Offset Voltage
V
SUPPLY
=
±1V,
I
Q
= 10μA, Unless Otherwise Specified
TEST
CONDITIONS
R
S
≤
100kΩ
TEMP
(°C)
+25
Full
ICL7612B
MIN
-
-
-
-
-
-
-
+0.6 to
-1.1
±0.98
±0.96
TYP
-
-
15
0.5
-
1.0
-
-
-
-
MAX
5
7
-
30
300
50
500
-
-
-
UNITS
mV
mV
μV/°C
pA
pA
pA
pA
V
V
V
SYMBOL
V
OS
Temperature Coefficient of V
OS
Input Offset Current
ΔV
OS
/ΔT R
S
≤
100kΩ
I
OS
-
+25
Full
Input Bias Current
I
BIAS
+25
Full
Extended Common Mode
Voltage Range
Output Voltage Swing
V
CMR
V
OUT
R
L
= 1MΩ
+25
+25
Full
4
FN2919.8
September 27, 2006
ICL7611, ICL7612
Electrical Specifications
PARAMETER
Large Signal Voltage Gain
V
SUPPLY
=
±1V,
I
Q
= 10μA, Unless Otherwise Specified
(Continued)
TEST
CONDITIONS
V
O
=
±0.1V,
R
L
= 1MΩ
TEMP
(°C)
+25
Full
Unity Gain Bandwidth
Input Resistance
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Input Referred Noise Voltage
Input Referred Noise Current
Supply Current
Slew Rate
Rise Time
Overshoot Factor
GBW
R
IN
CMRR
PSRR
e
N
i
N
I
SUPPLY
SR
t
r
OS
R
S
≤
100kΩ
R
S
≤
100kΩ
R
S
= 100Ω, f = 1kHz
R
S
= 100Ω, f = 1kHz
No Signal, No Load
A
V
= 1, C
L
= 100pF,
V
IN
= 0.2V
P-P
, R
L
= 1MΩ
V
IN
= 50mV, C
L
= 100pF R
L
= 1MΩ
V
IN
= 50mV, C
L
= 100pF, R
L
= 1MΩ
+25
+25
+25
+25
+25
+25
+25
+25
+25
+25
ICL7612B
MIN
-
-
-
-
-
-
-
-
-
-
-
-
TYP
90
80
0.044
10
12
80
80
100
0.01
6
0.016
20
5
MAX
-
-
-
-
-
-
-
-
15
-
-
-
UNITS
dB
dB
MHz
Ω
dB
dB
nV/√Hz
pA/√Hz
μA
V/μs
μs
%
SYMBOL
A
VOL
Schematic Diagram
I
Q
INPUT STAGE
SETTING STAGE
OUTPUT STAGE
V+
3k
BAL
Q
P1
V+
+INPUT
Q
N1
Q
N2
Q
P1
3k
900k
Q
P5
BAL
Q
P3
100k
Q
P4
Q
P9
C
FF
= 9pF
OUTPUT
V-
V+
C
C
= 33pF
Q
P6
Q
P7
Q
P8
6.3V
-INPUT
Q
N7
V-
Q
N3
Q
N4
Q
N5
Q
N8
V-
Q
N6
Q
N9
Q
N10
6.3V
Q
N11
V+
I
Q
SET
5
FN2919.8
September 27, 2006