IS43/46R86400D
IS43/46R16320D, IS43/46R32160D
16Mx32, 32Mx16, 64Mx8
512Mb DDR SDRAM
FEATURES
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VDD and VDDQ: 2.5V ± 0.2V (-5, -6)
VDD and VDDQ: 2.5V ± 0.1V (-4)
SSTL_2 compatible I/O
Double-data rate architecture; two data transfers
per clock cycle
Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
DQS is edge-aligned with data for READs and
centre-aligned with data for WRITEs
Differential clock inputs (CK and CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge;
data and data mask referenced to both edges of
DQS
Four internal banks for concurrent operation
Data Mask for write data. DM masks write data
at both rising and falling edges of data strobe
Burst Length: 2, 4 and 8
Burst Type: Sequential and Interleave mode
Programmable CAS latency: 2, 2.5 and 3
Auto Refresh and Self Refresh Modes
Auto Precharge
PRELIMINARY INFORMATION
SEPTEMBER 2010
DEVICE OVERVIEW
ISSI’s 512-Mbit DDR SDRAM achieves high speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 536,870,912-bit memory
array is internally organized as four banks of 128Mb to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 8-bit, 16-bit and 32-bit data word size
Input data is registered on the I/O pins on both edges
of Data Strobe signal(s), while output data is referenced
to both edges of Data Strobe and both edges of CLK.
Commands are registered on the positive edges of CLK.
An Auto Refresh mode is provided, along with a Self
Refresh mode. All I/Os are SSTL_2 compatible.
ADDRESS TABLE
Parameter
Configuration
16M x 32
4M x 32 x 4
banks
32M x 16
8M x 16 x 4
banks
BA0, BA1
A10/AP
64M x 8
16M x 8 x 4
banks
BA0, BA1
A10/AP
Bank Address BA0, BA1
Pins
Autoprecharge A8/AP
Pins
Row Address
Column
Address
8K(A0 – A12)
512(A0 – A7,
A9)
8K(A0 – A12) 8K(A0 – A12)
1K(A0 – A9)
8K / 64ms
8K / 16ms
2K(A0 – A9,
A11)
8K / 64ms
8K / 16ms
OPTIONS
• Configuration(s): 16Mx32, 32Mx16, and 64Mx8
• Package(s): 144 Ball BGA (x32), 66-pin TSOP-II
(x8, x16), and 60 Ball BGA (x8, x16)
• Lead-free package
• Temperature Range:
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Automotive, A1 (-40°C to +85°C)
Automotive, A2 (-40°C to +105°C)
Refresh Count
Com./Ind./A1 8K / 64ms
A2
8K / 16ms
KEY TIMING PARAMETERS
Speed Grade
-4
-5
x8, x16 only
F
ck
Max CL = 3
250 200
F
ck
Max CL = 2.5
–
167
F
ck
Max CL = 2
–
133
-6
Units
MHz
MHz
MHz
167
167
133
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can rea-
sonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-
tions unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. 00B
08/13/10
1
FPGA/CPLD
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