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74AC273

Description
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
Categorysemiconductor    logic   
File Size91KB,8 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
Download Datasheet Parametric Compare View All

74AC273 Overview

ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20

74AC273 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals20
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage5.5 V
Minimum supply/operating voltage4.5 V
Rated supply voltage5 V
Processing package descriptionLead FREE, SOIC-20
Lead-freeYes
EU RoHS regulationsYes
China RoHS regulationsYes
stateACTIVE
CraftsmanshipCMOS
packaging shapeRectangle
Package SizeSMALL OUTLINE
surface mountYes
Terminal formGULL WING
Terminal spacing1.27 mm
terminal coatingMATTE Tin
Terminal locationpair
Packaging MaterialsPlastic/Epoxy
Temperature levelINDUSTRIAL
seriesACT
Logic IC typeD flip-flop
Number of digits8
Output polarityTRUE
propagation delay TPD12 ns
Trigger typePOSITIVE edge
Max-Min frequency125 MHz
MC74AC273, MC74ACT273
Octal D Flip-Flop
The MC74AC273/74ACT273 has eight edge-triggered D−type
flip−flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip−flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the LOW−to−HIGH clock transition, is transferred
to the corresponding flip−flop’s Q output.
All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR input. The device is useful
for applications where the true output only is required and the Clock
and Master Reset are common to all storage elements.
Features
www.onsemi.com
20
SOIC−20WB
SUFFIX DW
CASE 751D
1
TSSOP−20
SUFFIX DT
CASE 948E
1
Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip−Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
Outputs Source/Sink 24 mA
′ACT273
Has TTL Compatible Inputs
These are Pb−Free Devices
V
CC
20
Q
7
19
D
7
18
D
6
17
Q
6
16
Q
5
15
D
5
14
D
4
13
Q
4
12
CP
11
20
PIN ASSIGNMENT
PIN
D
0
−D
7
MR
CP
Q
0
−Q
7
FUNCTION
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
MR
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
1
MR
2
Q
0
3
D
0
4
D
1
5
6
7
D
2
8
D
3
9
Q
3
10
GND
Q
1
Q
2
(Top View)
Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
Pinout: 20−Lead Packages Conductors
MODE SELECT-FUNCTION TABLE
Operating Mode
Reset (Clear)
Load
′1′
Load
′0′
Inputs
MR
L
H
H
CP
X
D
n
X
H
L
Outputs
Q
n
L
H
L
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
©
Semiconductor Components Industries, LLC, 2016
1
December, 2016 − Rev. 8
Publication Order Number:
MC74AC273/D

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74AC273 MC74AC273 MC74AC273_05 MC74ACT273 74ACT273 MC74ACT273MEL
Description ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20 ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20
Number of functions 1 1 1 1 1 1
Number of terminals 20 20 20 20 20 20
Maximum operating temperature 85 Cel 85 Cel 85 Cel 85 Cel 85 Cel 85 °C
Minimum operating temperature -40 Cel -40 Cel -40 Cel -40 Cel -40 Cel -40 °C
surface mount Yes Yes Yes Yes Yes YES
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal location pair pair pair pair pair DUAL
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
series ACT ACT ACT ACT ACT ACT
Number of digits 8 8 8 8 8 8
Output polarity TRUE TRUE TRUE TRUE TRUE TRUE
Trigger type POSITIVE edge POSITIVE edge POSITIVE edge POSITIVE edge POSITIVE edge POSITIVE EDGE
Maximum supply/operating voltage 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V -
Minimum supply/operating voltage 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V -
Rated supply voltage 5 V 5 V 5 V 5 V 5 V -
Processing package description Lead FREE, SOIC-20 Lead FREE, SOIC-20 Lead FREE, SOIC-20 Lead FREE, SOIC-20 Lead FREE, SOIC-20 -
Lead-free Yes Yes Yes Yes Yes -
EU RoHS regulations Yes Yes Yes Yes Yes -
China RoHS regulations Yes Yes Yes Yes Yes -
state ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE -
Craftsmanship CMOS CMOS CMOS CMOS CMOS -
packaging shape Rectangle Rectangle Rectangle Rectangle Rectangle -
Package Size SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE -
Terminal spacing 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm -
terminal coating MATTE Tin MATTE Tin MATTE Tin MATTE Tin MATTE Tin -
Packaging Materials Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy Plastic/Epoxy -
Logic IC type D flip-flop D flip-flop D flip-flop D flip-flop D flip-flop -
propagation delay TPD 12 ns 12 ns 12 ns 12 ns 12 ns -
Max-Min frequency 125 MHz 125 MHz 125 MHz 125 MHz 125 MHz -
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