EDB2432B4MA-1DIT-F-D datasheet, PDF

Datasheet> All Categories > storage> storage> EDB2432B4MA-1DIT-F-D

EDB2432B4MA-1DIT-F-D: DescriptionIC DRAM 2G PARALLEL 533MHZ; Categorystorage storage; File Size2MB，148 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

Download Datasheet Parametric Compare View All

EDB2432B4MA-1DIT-F-D Overview

IC DRAM 2G PARALLEL 533MHZ

EDB2432B4MA-1DIT-F-D Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Micron Technology
package instruction	VFBGA,
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Other features	SELF REFRESH; IT ALSO REQUIRES 1.8V NOM
JESD-30 code	R-PBGA-B134
JESD-609 code	e1
length	11.5 mm
memory density	2147483648 bit
Memory IC Type	DDR DRAM
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	134
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	64MX32
Package body material	PLASTIC/EPOXY
encapsulated code	VFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum seat height	1 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.3 V
Minimum supply voltage (Vsup)	1.14 V
Nominal supply voltage (Vsup)	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.65 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10 mm
Base Number Matches	1

Preview

Download Datasheet

View All

Embedded LPDDR2 SDRAM

Features

Embedded LPDDR2 SDRAM

EDB1316BD, EDB1332BD, EDB2432B4, EDB4064B4

Features

• Ultra low-voltage core and I/O power supplies

– V

DD2

= 1.14–1.30V

– V

DDCA

DDQ

= 1.14–1.30V

– V

DD1

= 1.70–1.95V

• Clock frequency range

– 533–10 MHz (data rate range: 1066–20 Mb/s/pin)

• Four-bit prefetch DDR architecture

• Eight internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on every CK edge

• Bidirectional/differential data strobe per byte of

data (DQS/DQS#)

• Programmable READ and WRITE latencies (RL/WL)

• Programmable burst lengths: 4, 8, or 16

• Per-bank refresh for concurrent operation

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock stop capability

• RoHS-compliant, “green” packaging

Table 1: Key Timing Parameters

Speed

Grade

Clock Rate

(MHz)

533

Data Rate

(Mb/s/pin)

1066

Options

• Density/Page Size

– 1Gb/2KB - single die

– 2Gb/2KB - dual die

– 4Gb/2KB - quad die

• Organization

– x16

– x32

– x64

• V

DD2

: 1.2V

• Revision

– Single die

– Multi-die

• FBGA “green” package

– 134-ball FBGA

– 134-ball multi-die FBGA

– 168-ball FBGA

for PoP

– 216-ball multi-die FBGA

for PoP

• Timing – cycle time

– 1.875ns @ RL = 8

• Operating temperature range

– From –30°C to +85°C

– From –40°C to +85°C

Marking

-1D

(Blank)

Table 2: S4 Configuration Addressing

Architecture

Die configura-

tion

Row addressing

Column ad-

dressing

Number of die

Die per rank

Ranks per chan-

nel

Note:

64 Meg x 16

8 Meg x 16 x 8 banks

8K (A[12:0])

1K (A[9:0])

32 Meg x 32

4 Meg x 32 x 8 banks

8K (A[12:0])

512 (A[8:0])

64 Meg x 32

64 Meg x 64

2 x 8 Meg x 16 x 8 banks 4 x 8 Meg x 16 x 8 banks

8K (A[12:0])

1K (A[9:0])

8K (A[12:0])

1K (A[9:0])

1. A channel is a complete LPDRAM interface, including command/address and data pins.

X26P4QTWDSPK-13-10152

u98m_lpddr2_embedded.pdf - Rev. E 11/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Embedded LPDDR2 SDRAM

Features

Contents

General Description ......................................................................................................................................... 9

General Notes .............................................................................................................................................. 9

Specifications ........................................................................................................................................... 10

Package Block Diagrams ................................................................................................................................. 16

Package Dimensions ....................................................................................................................................... 18

Ball Assignments ............................................................................................................................................ 21

Ball Descriptions ............................................................................................................................................ 25

Functional Description ................................................................................................................................... 26

Power-Up ....................................................................................................................................................... 27

Initialization After RESET (Without Voltage Ramp) ...................................................................................... 29

Power-Off ....................................................................................................................................................... 29

Uncontrolled Power-Off .............................................................................................................................. 30

Mode Register Definition ................................................................................................................................ 30

Mode Register Assignments and Definitions ................................................................................................ 30

ACTIVATE Command ..................................................................................................................................... 41

8-Bank Device Operation ............................................................................................................................ 41

Read and Write Access Modes ......................................................................................................................... 42

Burst READ Command ................................................................................................................................... 42

READs Interrupted by a READ ..................................................................................................................... 49

Burst WRITE Command .................................................................................................................................. 49

WRITEs Interrupted by a WRITE ................................................................................................................. 52

BURST TERMINATE Command ...................................................................................................................... 52

Write Data Mask ............................................................................................................................................. 54

PRECHARGE Command ................................................................................................................................. 55

READ Burst Followed by PRECHARGE ......................................................................................................... 56

WRITE Burst Followed by PRECHARGE ....................................................................................................... 57

Auto Precharge ........................................................................................................................................... 58

READ Burst with Auto Precharge ................................................................................................................. 58

WRITE Burst with Auto Precharge ............................................................................................................... 59

REFRESH Command ...................................................................................................................................... 61

REFRESH Requirements ............................................................................................................................. 67

SELF REFRESH Operation ............................................................................................................................... 69

Partial-Array Self Refresh – Bank Masking .................................................................................................... 70

Partial-Array Self Refresh – Segment Masking .............................................................................................. 71

MODE REGISTER READ ................................................................................................................................. 72

Temperature Sensor ................................................................................................................................... 74

DQ Calibration ........................................................................................................................................... 76

MODE REGISTER WRITE Command ............................................................................................................... 78

MRW RESET Command .............................................................................................................................. 78

MRW ZQ Calibration Commands ................................................................................................................ 79

ZQ External Resistor Value, Tolerance, and Capacitive Loading ..................................................................... 81

Power-Down .................................................................................................................................................. 81

Deep Power-Down ......................................................................................................................................... 88

Input Clock Frequency Changes and Stop Events ............................................................................................. 89

Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 89

Input Clock Frequency Changes and Clock Stop with CKE HIGH .................................................................. 90

NO OPERATION Command ............................................................................................................................ 90

Simplified Bus Interface State Diagram ........................................................................................................ 90

Truth Tables ................................................................................................................................................... 92

Electrical Specifications ................................................................................................................................. 100

X26P4QTWDSPK-13-10152

u98m_lpddr2_embedded.pdf - Rev. E 11/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Embedded LPDDR2 SDRAM

Features

Absolute Maximum Ratings ....................................................................................................................... 100

Input/Output Capacitance ......................................................................................................................... 100

Electrical Specifications – I

Specifications and Conditions ........................................................................... 101

AC and DC Operating Conditions ................................................................................................................... 104

AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 106

REF

Tolerances ......................................................................................................................................... 107

Input Signal .............................................................................................................................................. 108

AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 110

Single-Ended Requirements for Differential Signals .................................................................................... 111

Differential Input Crosspoint Voltage ......................................................................................................... 113

Input Slew Rate ......................................................................................................................................... 114

Output Characteristics and Operating Conditions ........................................................................................... 114

Single-Ended Output Slew Rate .................................................................................................................. 115

Differential Output Slew Rate ..................................................................................................................... 116

HSUL_12 Driver Output Timing Reference Load ......................................................................................... 118

Output Driver Impedance .............................................................................................................................. 118

Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 119

Output Driver Temperature and Voltage Sensitivity ..................................................................................... 120

Output Impedance Characteristics Without ZQ Calibration ......................................................................... 120

Clock Specification ........................................................................................................................................ 123

CK(abs),

CH(abs), and

CL(abs) ................................................................................................................ 124

Clock Period Jitter .......................................................................................................................................... 124

Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 124

Cycle Time Derating for Core Timing Parameters ........................................................................................ 125

Clock Cycle Derating for Core Timing Parameters ....................................................................................... 125

Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 125

Clock Jitter Effects on READ Timing Parameters .......................................................................................... 125

Clock Jitter Effects on WRITE Timing Parameters ........................................................................................ 126

Refresh Requirements .................................................................................................................................... 127

AC Timing ..................................................................................................................................................... 128

CA and CS# Setup, Hold, and Derating ........................................................................................................... 134

Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 141

Revision History ............................................................................................................................................ 148

Rev. E – 10/16 ............................................................................................................................................ 148

Rev. D – 5/16 ............................................................................................................................................. 148

Rev. C – 2/16 .............................................................................................................................................. 148

Rev. B – 11/15 ............................................................................................................................................ 148

Rev. A – 06/15 ............................................................................................................................................ 148

X26P4QTWDSPK-13-10152

u98m_lpddr2_embedded.pdf - Rev. E 11/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Embedded LPDDR2 SDRAM

Features

List of Figures

Figure 1: LPDDR2 Part Numbering ................................................................................................................... 2

Figure 2: V

DD1

Typical Self-Refresh Current vs. Temperature (Per Die) .............................................................. 15

Figure 3: V

DD2

Typical Self-Refresh Current vs. Temperature (Per Die) .............................................................. 15

Figure 4: Single Die Single Rank, Single Channel Package Block Diagram ......................................................... 16

Figure 5: Dual Die Single Rank, Single Channel Package Block Diagram ........................................................... 16

Figure 6: Quad Die Dual Rank, Dual Channel Package Block Diagram ............................................................. 17

Figure 7: 134-Ball VFBGA – 10mm x 11.5mm (Package Code: BH, MA) ............................................................. 18

Figure 8: 168-Ball WFBGA – 12mm x 12mm (Package Code: PC) ...................................................................... 19

Figure 9: 216-Ball WFBGA – 12mm x 12mm (Package Code: PB) ...................................................................... 20

Figure 10: 134-Ball FBGA (x16) ....................................................................................................................... 21

Figure 11: 134-Ball FBGA (x32) ....................................................................................................................... 22

Figure 12: 168-Ball FBGA ............................................................................................................................... 23

Figure 13: 216-Ball FBGA ............................................................................................................................... 24

Figure 14: Functional Block Diagram ............................................................................................................. 26

Figure 15: Voltage Ramp and Initialization Sequence ...................................................................................... 29

Figure 16: ACTIVATE Command .................................................................................................................... 41

Figure 17:

FAW Timing (8-Bank Devices) ....................................................................................................... 42

Figure 18: READ Output Timing –

DQSCK (MAX) ........................................................................................... 43

Figure 19: READ Output Timing –

DQSCK (MIN) ........................................................................................... 43

Figure 20: Burst READ – RL = 5, BL = 4,

DQSCK >

CK ..................................................................................... 44

Figure 21: Burst READ – RL = 3, BL = 8,

DQSCK <

CK ..................................................................................... 44

Figure 22:

DQSCKDL Timing ........................................................................................................................ 45

Figure 23:

DQSCKDM Timing ....................................................................................................................... 46

Figure 24:

DQSCKDS Timing ......................................................................................................................... 47

Figure 25: Burst READ Followed by Burst WRITE – RL = 3, WL = 1, BL = 4 ......................................................... 48

Figure 26: Seamless Burst READ – RL = 3, BL = 4,

CCD = 2 .............................................................................. 48

Figure 27: READ Burst Interrupt Example – RL = 3, BL = 8,

CCD = 2 ................................................................. 49

Figure 28: Data Input (WRITE) Timing ........................................................................................................... 50

Figure 29: Burst WRITE – WL = 1, BL = 4 ......................................................................................................... 50

Figure 30: Burst WRITE Followed by Burst READ – RL = 3, WL = 1, BL = 4 ......................................................... 51

Figure 31: Seamless Burst WRITE – WL = 1, BL = 4,

CCD = 2 ............................................................................ 51

Figure 32: WRITE Burst Interrupt Timing – WL = 1, BL = 8,

CCD = 2 ................................................................ 52

Figure 33: Burst WRITE Truncated by BST – WL = 1, BL = 16 ............................................................................ 53

Figure 34: Burst READ Truncated by BST – RL = 3, BL = 16 ............................................................................... 54

Figure 35: Data Mask Timing ......................................................................................................................... 54

Figure 36: Write Data Mask – Second Data Bit Masked .................................................................................... 55

Figure 37: READ Burst Followed by PRECHARGE – RL = 3, BL = 8, RU(

RTP(MIN)/

CK) = 2 ................................ 56

Figure 38: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU(

RTP(MIN)/

CK) = 3 ................................ 57

Figure 39: WRITE Burst Followed by PRECHARGE – WL = 1, BL = 4 .................................................................. 58

Figure 40: READ Burst with Auto Precharge – RL = 3, BL = 4, RU(

RTP(MIN)/

CK) = 2 ........................................ 59

Figure 41: WRITE Burst with Auto Precharge – WL = 1, BL = 4 .......................................................................... 60

Figure 42: Regular Distributed Refresh Pattern ............................................................................................... 64

Figure 43: Supported Transition from Repetitive REFRESH Burst .................................................................... 65

Figure 44: Nonsupported Transition from Repetitive REFRESH Burst .............................................................. 66

Figure 45: Recommended Self Refresh Entry and Exit ..................................................................................... 67

Figure 46:

SRF Definition .............................................................................................................................. 68

Figure 47: All-Bank REFRESH Operation ........................................................................................................ 68

Figure 48: Per-Bank REFRESH Operation ....................................................................................................... 69

Figure 49: SELF REFRESH Operation .............................................................................................................. 70

Figure 50: MRR Timing – RL = 3,

MRR = 2 ...................................................................................................... 72

X26P4QTWDSPK-13-10152

u98m_lpddr2_embedded.pdf - Rev. E 11/16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

EDB2432B4MA-1DIT-F-D Related Products

	EDB2432B4MA-1DIT-F-D	EDB2432B4MA-1DIT-F-R	EDB2432B4MA-1DIT-F	EDB4064B4PB-1DIT-F-D	EDB4064B4PB-1DIT-F-D TR	EDB4064B4PB-1DIT-F-R TR	EDB4064B4PB-1DIT-F-R	EDB4064B4PB-1D-F-D	EDB4064B4PB-1D-F-R TR
Description	IC DRAM 2G PARALLEL 533MHZ	DDR DRAM, 64MX32, CMOS, PBGA134, VFBGA-134	DDR DRAM, 64MX32, CMOS, PBGA134, VFBGA-134	IC DRAM 4G PARALLEL 533MHZ	IC DRAM 4G PARALLEL 533MHZ	IC DRAM 4G PARALLEL 216WFBGA	IC DRAM 4G PARALLEL 216WFBGA	IC DRAM 4G PARALLEL 216WFBGA	IC DRAM 4G PARALLEL 216WFBGA
technology	CMOS	CMOS	CMOS	SDRAM - Mobile LPDDR2	SDRAM - Mobile LPDDR2	SDRAM - Mobile LPDDR2	SDRAM - Mobile LPDDR2	SDRAM - Mobile LPDDR2	SDRAM - Mobile LPDDR2
memory type	-	-	-	Volatile	Volatile	Volatile	Volatile	Volatile	Volatile
memory format	-	-	-	DRAM	DRAM	DRAM	DRAM	DRAM	DRAM
storage	-	-	-	4Gb （64M x 64）	4Gb （64M x 64）	4Gb （64M x 64）	4Gb （64M x 64）	4Gb （64M x 64）	4Gb （64M x 64）
Clock frequency	-	-	-	533MHz	533MHz	533MHz	533MHz	533MHz	533MHz
memory interface	-	-	-	in parallel	in parallel	in parallel	in parallel	in parallel	in parallel
Voltage - Power	-	-	-	1.14 V ~ 1.95 V	1.14 V ~ 1.95 V	1.14 V ~ 1.95 V	1.14 V ~ 1.95 V	1.14 V ~ 1.95 V	1.14 V ~ 1.95 V
Operating temperature	-	-	-	-40°C ~ 85°C（TC）	-40°C ~ 85°C（TC）	-40°C ~ 85°C（TC）	-40°C ~ 85°C（TC）	-30°C ~ 85°C（TC）	-30°C ~ 85°C（TC）

Recommended Resources

Resistance furnace drive and measurement circuit

Negative resistance dielectric oscillator and equivalent circuit

Pyroelectric infrared induction automatic light circuit (1)

Another type uses autotransformer and time relay starting control circuit

Ray detection circuit

150V regulated power supply circuit

What is the difference between stepper motor driver chip and DC motor driver chip?: What is the difference between a stepper motor driver chip and a DC motor driver chip? In terms of input and output? Can a stepper motor driver directly drive a DC motor? What is a linear drive and wh...; shijizai Motor Drive Control（Motor Control）

Application of infrared remote control in automobiles: Abstract : This paper briefly introduces the principle of infrared remote control transmitting and receiving system, and gives a clever implementation method of using 89C2051 as a decoder of remote co...; frozenviolet Automotive Electronics

A Review of Frequency Synthesizer Architecture Design for Wireless Communication Systems: Abstract: Based on the introduction of the main design indicators of frequency synthesizers in the field of wireless communication, the structural designs of various frequency synthesizers are compare...; JasonYoo RF/Wirelessly

Research and Design of MP3 Player Based on DSP Technology: Please give me some advice, thank you in advance....; 646322543 DSP and ARM Processors

Newbie help: Does anyone know if there is a problem with the second half of the program? Use Proteus to simulate the key k3 does not work K1 BIT P2.0 K2 BIT P2.1 K3 BIT P2.2 ORG 0030H MAIN:MOV R0,#0 MOV P1,#0 MOV ...; putao 51mcu

CPU frequency == performance?: A brief discussion on the CPU's execution efficiency and internal execution pipelineOriginal author: Shanghai Yao ZhenWhy does the AMD 2500+ processor with an actual frequency of only 1.8G run faster ...; jackping025 Embedded System

A temperature tester based on FM20L08

1 Introduction The high temperature tester is mainly used for temperature tracking measurement and data acquisition during the heating process. By systematically analyzing the test data, the...[Details]
Design of high-efficiency LED road lighting driver

As LEDs continue to improve in almost every aspect of performance and cost, LED lighting is being used in an increasingly wide range of applications, among which LED street lights are a focus of in...[Details]
Power management poses challenges

As cellular phones become more advanced, the power consumption of the system during operation and the power consumption during standby are also increasing. Therefore, the power management design of...[Details]
Application of MEMS Technology in Uncooled Infrared Detectors

1 Introduction As an emerging microfabrication technology, micro-electromechanical system (MEMS) technology has begun to be applied in various fields. It can integrate functions such as inform...[Details]
PROFIBUS bus bridge PB-B-RS232\485 product application

Product series: PB-B-RS232/485 interface (hereinafter sometimes referred to as "interface") is a product in the PROFIBUS bus bridge series. The main purpose of the bridge series ...[Details]
Modern batteries in all their forms

Flooded Batteries This battery developed in Germany can be used to power flashlights, strobe lights and toys as long as it is filled with water. This battery can be stored for 50 years and can...[Details]
Design and application of interface between graphic dot matrix LCD module and 51 single chip microcomputer

Introduction Liquid crystal, as a display device, is widely used in low-power products such as instruments, meters, and electronic equipment with its unique advantages. In the past, the displ...[Details]
Composition and precautions of solar LED lighting system

Today, with energy becoming increasingly scarce, the utilization of natural energy has become the focus of people's attention. Among various natural energies, the endless solar energy is highly fav...[Details]
Energy saving analysis of LED display screen using D5026A

D5026A is a driver IC designed by Shanghai Debei Electronics for energy-saving LED display screens. Its design concept is energy-saving and compatible with existing solutions, that is, it can be ...[Details]
Can solar LED lighting in highway tunnels replace existing conventional lighting systems?

1 Introduction With the rapid economic development, my country's electricity demand has been growing at a rate of more than 20% per year. According to the current economic development trend an...[Details]
Unexpected future of cars: power lithium batteries

The most important components of new energy electric vehicles are power batteries, electric motors and energy conversion control systems. The power battery must achieve high performance such as fas...[Details]
Introduction of common rechargeable batteries

With the popularity of digital appliances, rechargeable batteries can be seen everywhere in people's daily lives and have become one of the indispensable daily necessities. This article gives ...[Details]
Application of USB Communication Technology in Automatic Test System

1 Introduction Automatic Test System The ATS (Automatic Test System) integrates all the stimulus and measurement equipment required for testing. The computer efficiently comp...[Details]
Application of PROFIBUS-DP in ABB AC450 System

0 Introduction PROFIBUS is an open digital communication system with a wide range of applications, which has been included in the international standards IEC 61158 and IEC 61784. Since the gen...[Details]
Analysis of automotive TPMS dedicated sensor technology

TPMS is the abbreviation of "Tire Pressure Monitoring System". It is mainly used to automatically monitor the tire pressure in real time when the car is driving, and to alarm for tire leakage and l...[Details]

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components