19-6080; Rev 11/11
www.dalsemi.com
DS1315
Phantom Time Chip
FEATURES
Real-Time Clock Keeps Track of Hundredths
of Seconds, Seconds, Minutes, Hours, Days,
Date of the Month, Months, and Years
Automatic Leap Year Correction Valid Up to
2100
No Address Space Required to Communicate
with RTC
Provides Nonvolatile Controller Functions for
Battery Backup of SRAM
Supports Redundant Battery Attachment for
High-Reliability Applications
Full ±10% V
CC
Operating Range
+3.3V or +5V Operation
Industrial (-40°C to +85°C) Operating
Temperature Ranges Available
- 32.768kHz Crystal Connection
- Write Enable
- Battery 1 Input
- Ground
- Data Input
- Data Output
- ROM/RAM Mode Select
- Chip Enable Output
- Chip Enable Input
- Output Enable
- Reset
- Battery 2 Input
- Switched Supply Output
- Power Supply Input
DESCRIPTION
The DS1315 Phantom Time Chip is a
combination of a CMOS timekeeper and a
nonvolatile memory controller. In the absence of
power, an external battery maintains the
timekeeping operation and provides power for a
CMOS static RAM. The watch keeps track of
hundredths of seconds, seconds, minutes, hours,
day, date, month, and year information. The last
day of the month is automatically adjusted for
months with fewer than 31 days, including leap
year correction. The watch operates in one of two
formats: a 12-hour mode with an AM/PM
indicator or a 24-hour mode. The nonvolatile
controller supplies all the necessary support
circuitry to convert a CMOS RAM to a
nonvolatile memory. The DS1315 can be
interfaced with either RAM or ROM without
leaving gaps in memory.
PIN DESCRIPTION
X1, X2
WE
PIN CONFIGURATIONS
X1
X2
WE
BAT1
GND
D
Q
GND
1
2
3
4
5
6
7
8
16
V
CC1
V
CC0
BAT2
RST
OE
CEI
CEO
ROM/RAM
DS1315
15
14
13
12
11
10
9
BAT1
GND
D
Q
ROM/
RAM
CEO
CEI
BAT2
V
CC0
V
CC1
OE
RST
PDIP (300 mils)
Pin Configurations continued at end of data sheet.
1 of 21
DS1315 Phantom Time Chip
ORDERING INFORMATION
PART
DS1315-33+
DS1315N-33+
DS1315-5+
DS1315N-5+
DS1315E-33+
DS1315EN-33+
DS1315EN-33+T&R
DS1315E-5+
DS1315EN-5+
DS1315EN-5+T&R
DS1315S-33+
DS1315SN-33+
DS1315S-5+
DS1315SN-5+
DS1315S-5+T&R
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
VOLTAGE
PIN-PACKAGE
(V)
3.3
16 PDIP (300 mils)
3.3
5
5
3.3
3.3
3.3
5
5
5
3.3
3.3
5
5
5
16 PDIP (300 mils)
16 PDIP (300 mils)
16 PDIP (300 mils)
20 TSSOP (4.4mm)
20 TSSOP (4.4mm)
20 TSSOP (4.4mm)
20 TSSOP (4.4mm)
20 TSSOP (4.4mm)
20 TSSOP (4.4mm)
16 SO (300 mils)
16 SO (300 mils)
16 SO (300 mils)
16 SO (300 mils)
16 SO (300 mils)
TOP MARK*
DS1315 336
DS1315 336
DS1315 56
DS1315 56
DS1315E XXXX-336
DS1315E XXXX-336
DS1315E XXXX-336
DS1315E XXXX-56
DS1315E XXXX-56
DS1315E XXXX-56
DS1315 336
DS1315 336
DS1315 56
DS1315S 56
DS1315S 56
+
Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*A
“+” symbol located anywhere on the top mark indicates a lead-free device. An “N” located in the bottom right-hand corner of the top of the
package denotes an industrial device. “xxxx” can be any combination of characters.
2 of 21
DS1315 Phantom Time Chip
Figure 1. Block Diagram
3 of 21
DS1315 Phantom Time Chip
Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits
which must be matched by executing 64 consecutive write cycles containing the proper data on data in
(D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the
chip enable output pin (
CEO
).
After recognition is established, the next 64 read or write cycles either extract or update data in the Time
Chip and
CEO
remains high during this time, disabling the connected memory.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable input (
CEI
), output enable (
OE
), and write enable (
WE
). Initially, a read cycle using the
CEI
and
OE
control of the Time Chip starts the pattern recognition sequence by moving pointer to the
first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the
CEI
and
WE
control of the Time Chip. These 64 write cycles are used only to gain access to the Time Chip.
When the first write cycle is executed, it is compared to bit 1 of the 64-bit comparison register. If a match
is found, the pointer increments to the next location of the comparison register and awaits the next write
cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If
a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the
comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as
described above until all the bits in the comparison register have been matched. (This bit pattern is shown
in Figure 2). With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the
timekeeping registers may proceed. The next 64 cycles will cause the Time Chip to either receive data on
D, or transmit data on Q, depending on the level of
OE
pin or the
WE
pin. Cycles to other locations
outside the memory block can be interleaved with
CEI
cycles without interrupting the pattern recognition
sequence or data transfer sequence to the Time Chip.
A standard 32.768kHz quartz crystal can be directly connected to the DS1315 via pins 1 and 2 (X1, X2).
The crystal selected for use should have a specified load capacitance (C
L
) of 6 pF. For more information
on crystal selection and crystal layout considerations, refer to Application Note 58:
Crystal
Considerations with Maxim Real-Time Clocks (RTCs).
Operation
4 of 21
DS1315 Phantom Time Chip
Figure 2. Time Chip Comparison Register Definition
Note:
The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being
accidentally duplicated and causing inadvertent entry to the Phantom Time Chip are less than 1 in 10
19
.
5 of 21
京公网安备 11010802033920号
EEWORLD
