EEWORLDEEWORLDEEWORLD

Part Number

Search

C8PPG-4036G

Description
DIP CABLE - CDP40G/AE40G/CDP40G
CategoryWire/cable   
File Size195KB,1 Pages
ManufacturerCW Industries
Websitehttp://www.cwind.com
Environmental Compliance
Download Datasheet Parametric View All

C8PPG-4036G Overview

DIP CABLE - CDP40G/AE40G/CDP40G

C8PPG-4036G Parametric

Parameter NameAttribute value
Connector typeDIP to DIP, reverse
Number of pins40
Number of rows2
Pitch - Connector0.100"(2.54mm)
Spacing - Cable0.050"(1.27mm)
length3.00'(914.40mm)
characteristic-
colorgray, banded
shieldNo shielding
useJack (0.6"), onboard
Cable terminationIDC
Contact platinggold
Contact plating thickness10.0µin(0.25µm)
DIP Cable Assemblies
Double Ended Style 8
DIP Connector without Strain Relief shown
Pin #1 on connector is connected to 2nd conductor on cable
Also available in the following version:
DIP Connector with Strain Relief Strap
C8RR
-
□□□□□
-ND
TI group-purchased chip DIY - Part 1: ADS8332
[i=s]This post was last edited by dontium on 2015-1-23 13:02[/i]I bought the chip from a group purchase, and I was itching to make one. Later, I printed a PCB. For details, see: bbs.eeworld../thread-3...
dontium Analogue and Mixed Signal
The high level output of Mega8 IO port is about 1.5V, and the low level output is about 0.3V. Please discuss it together.
[i=s] This post was last edited by huanjun123 on 2014-11-6 15:19 [/i] I made a minimum system based on mega8. When testing, the IO port high-level output was about 1.5V and the low-level output was ab...
huanjun123 Microchip MCU
The circuit board ran for about 2 hours before it broke down
Hello everyone: I recently made 5 boards, and a strange problem occurred during the copy machine. The function of the board is to record data through the serial port, with an operating system. When ru...
tianweiming9527 Embedded System
fpga phase locked loop demodulation FM
Someone previously posted a document (vhdl) about FPGA phase-locked loops from the Japanese FPGA competition. I referred to it, changed it to Verilog, and used ModelSim to give the same simulation res...
路人甲1 FPGA/CPLD
How to use the Security Erase Unit command in the ATA protocol?
I am currently working on hard disk data destruction, using the SST55LD019 (020) hard disk controller. When executing the Security Erase Unit command 0XF4 in the ATA protocol, the value returned by St...
longeteng Embedded System
The computer won't start. The cursor keeps blinking!
My computer suddenly won’t start up! I can enter the BIOS, and the connection of the hard disk and memory is basically fine! When I start up, I enter the motherboard information interface! It should b...
自由女神 Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2112  2670  1351  543  670  43  54  28  11  14 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号