Titl
®
SPS-1616
™
Datasheet
Secure Packet Switch
April 4, 2016
Table of Contents
Table of Contents
Introduction .............................................................................................................................................4
Additional Resources ..............................................................................................................................4
Document Conventions and Definitions ..................................................................................................4
Revision History ......................................................................................................................................4
1
2
3
4
5
6
Device Overview............................................................................................................................6
Features ........................................................................................................................................6
Block Diagram ...............................................................................................................................8
Device Description.........................................................................................................................8
Functional Overview ......................................................................................................................9
Interface Overview.......................................................................................................................10
S-RIO Ports .................................................................................................................................10
I2C Bus........................................................................................................................................10
JTAG TAP Port ............................................................................................................................10
Interrupt (IRQ_N).........................................................................................................................10
Reset (RST_N) ............................................................................................................................10
Clock (REF_CLK_P/N) ................................................................................................................10
Rext (REXT_N/P) ........................................................................................................................11
Speed Select (SPD[2:0]) .............................................................................................................11
Quadrant Config (QCFG[7:0]) .....................................................................................................11
Port Disable (PD[15:0]_N) ...........................................................................................................11
Frequency Select (FSEL[1:0]) .....................................................................................................11
Multicast (MCAST) ......................................................................................................................11
Configuration Pins .......................................................................................................................12
Speed Select Pins SPD[2:0]........................................................................................................12
Quadrant Configuration Pins QCFG[7:0].....................................................................................13
Absolute Maximum Ratings.........................................................................................................16
Recommended Operating Conditions .........................................................................................17
AC Test Conditions ......................................................................................................................18
Power Consumption ....................................................................................................................20
I
2
C Bus ........................................................................................................................................21
I
2
C Master Mode and Slave Mode ..............................................................................................21
I
2
C Device Address .....................................................................................................................21
Signaling......................................................................................................................................22
Read/Write Figures......................................................................................................................23
I
2
C DC Electrical Specifications ..................................................................................................25
I
2
C AC Electrical Specifications...................................................................................................26
I
2
C Timing Waveforms.................................................................................................................27
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8
9
10
11
12
Interrupt (IRQ_N) Electrical Specifications ..................................................................................27
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April 4, 2016
Integrated Device Technology, Inc.
Table of Contents
14
15
Configuration (Static) Pin Specification .......................................................................................28
S-RIO Ports .................................................................................................................................29
Overview......................................................................................................................................29
Definition of Amplitude and Swing...............................................................................................29
1.25, 2.5, and 3.125 Gbaud LP-Serial Links................................................................................31
Level I Electrical Specification .....................................................................................................31
5 and 6.25 Gbaud LP-Serial Links...............................................................................................38
Level II Electrical Specifications ..................................................................................................38
Reference Clock ..........................................................................................................................48
Reference Clock Electrical Specifications ...................................................................................48
Reset (RST_N) Specification.......................................................................................................50
JTAG Interface.............................................................................................................................51
Description...................................................................................................................................51
IEEE 1149.1 (JTAG) and IEEE 1149.6 (AC Extest) Compliance .................................................51
System Logic TAP Controller Overview.......................................................................................51
Signal Definitions.........................................................................................................................52
Test Data Register (DR) ..............................................................................................................53
Boundary Scan Registers............................................................................................................53
Instruction Register (IR)...............................................................................................................56
EXTEST.......................................................................................................................................57
Configuration Register Access ....................................................................................................59
JTAG DC Electrical Specifications...............................................................................................61
JTAG AC Electrical Specifications...............................................................................................62
JTAG Timing Waveforms.............................................................................................................62
Pinout and Pin Listing..................................................................................................................63
Pinout — Top View ......................................................................................................................63
Pin Listing ....................................................................................................................................64
Package Specifications ...............................................................................................................69
Package Physical Specifications .................................................................................................69
Package Drawings.......................................................................................................................70
Thermal Characteristics...............................................................................................................71
Ordering Information....................................................................................................................73
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17
18
19
20
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SPS-1616 Datasheet
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April 4, 2016
Integrated Device Technology, Inc.
About This Document
Introduction
The
SPS-1616 Datasheet
provides hardware information about the SPS-1616, such as electrical and
packaging characteristics. It is intended for hardware engineers who are designing system interconnect
applications with the device.
Additional Resources
The
SPS-1616 User Manual
describes the functionality and configuration capabilities of the device. In
addition, there are many other resources available that support the SPS-1616. For more information,
please contact IDT for support.
Document Conventions and Definitions
This document uses the following conventions and definitions:
•
To indicate signal states:
–
Differential signals use the suffix “_P” to indicate the positive half of a differential pair.
–
Differential signals use the suffix “_N” to indicate the negative half of a differential pair.
–
Non-differential signals use the suffix “_N” to indicate an active-low state.
•
•
To define buses, the most significant bit (MSB) is on the left and least significant bit (LSB) is on the right.
No leading zeros are included.
To represent numerical values, either decimal, binary, or hexadecimal formats are used. The binary
format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:
0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
Unless otherwise denoted, a byte refers to an 8-bit quantity; a word refers to a 32-bit quantity, and a
double word refers to an 8-byte (64-bit) quantity. This is in accordance with RapidIO convention.
A bit is set when its value is 0b1. A bit is cleared when its value is 0b0.
A read-only register, bit, or field is one that can be read but not modified.
This symbol indicates important configuration information or suggestions.
•
•
•
This symbol indicates procedures or operating levels that may result in misuse or damage to the
device.
Revision History
April 4, 2016
•
•
•
•
Added an R_X2 symbol to
Table 20
Added an HMG part number to
Ordering Information
Updated
Heat Sink Requirement and Analysis
Completed several minor improvements
July 25, 2013
SPS-1616 Datasheet
4
April 4, 2016
Integrated Device Technology, Inc.
About This Document
June 12, 2013
•
•
•
•
•
•
Updated the note associated with
VDD3A
(pin T18)
Changed the maximum 3.3V supply requirement to 3.47V in Table 6 and note 2 below the table
Updated the REF_CLK parameter in Table 29 to +/-50 ppm
Added two cautionary notes about lane reordering to
Pin Listing
Loosened the Clock Input signal rise/fall minimum time specification
Added an additional note to the power sequencing requirements
June 8, 2012
December 9, 2011
October 27, 2011
SPS-1616 Datasheet
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April 4, 2016
Integrated Device Technology, Inc.
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