FLLXT971ABC.A4-834103 datasheet, PDF

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FLLXT971ABC.A4-834103: DescriptionIC TXRX ETHERNET 100MBPS 64BGA; CategoryWireless rf/communication Telecom circuit; File Size1MB，96 Pages; ManufacturerInphi Corporation

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FLLXT971ABC.A4-834103 Overview

IC TXRX ETHERNET 100MBPS 64BGA

FLLXT971ABC.A4-834103 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Inphi Corporation
package instruction	LFBGA, BGA64,8X8,32
Reach Compliance Code	compliant
data rate	100000 Mbps
JESD-30 code	S-PBGA-B64
length	7 mm
Number of functions	1
Number of terminals	64
Transceiver quantity	1
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA64,8X8,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.36 mm
Maximum slew rate	0.11 mA
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7 mm

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Cortina Systems

LXT971A Single-Port

10/100 Mbps PHY Transceiver

Datasheet

The Cortina Systems

LXT971A Single-Port 10/100 Mbps PHY Transceiver (LXT971A PHY) directly

supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII)

for easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A PHY is IEEE compliant,

and provides a Low Voltage Positive Emitter Coupled Logic (LVPECL) interface for use with 100BASE-

FX fiber networks. The LXT971A PHY supports full-duplex operation at 10 Mbps and 100 Mbps.

Operating conditions for the LXT971A PHY can be set using auto-negotiation, parallel detection, or

manual control. The LXT971A PHY is fabricated with an advanced CMOS process and requires only a

single 2.5/3.3 V power supply. (This Datasheet also supports the LXT971 PHY.)

Applications

Combination 10BASE-T/100BASE-TX or

100BASE-FX Network Interface Cards (NICs)

Network printers

10/100 Mbps PCMCIA cards

Cable Modems and Set-Top Boxes

Product Features

3.3 V Operation

Low power consumption (300 mW typical)

Low-power “Sleep” mode

10BASE-T and 100BASE-TX using a single RJ-

45 connection

IEEE 802.3-compliant 10BASE-T or 100BASE-

TX ports with integrated filters

Auto-negotiation and parallel detection

MII interface with extended register capability

Robust baseline wander correction

Carrier Sense Multiple Access / Collision

Detection (CSMA/CD) or full-duplex operation

JTAG boundary scan

MDIO serial port or hardware pin configurable

100BASE-FX fiber-optic capable

Integrated, programmable LED drivers

64-ball Plastic Ball Grid Array (PBGA) or 64-pin

Quad Flat Package (LQFP)

LXT971ABC - Commercial (0

to 70

C amb.)

LXT971ABE - Extended (-40

to 85

C amb.)

LXT971ALC - Commercial (0

to 70

C amb.)

LXT971ALE - Extended (-40

to 85

C amb.)

LXT972ALC - Commercial (0° to 70 °C amb.)

LXT971A PHY

Datasheet

249414, Revision 5.2

13 September 2007

Contents

1.0

Introduction to This Document .................................................................................................. 10

1.1

1.2

2.0

3.0

4.0

5.0

Document Overview ...........................................................................................................10

Related Documents ............................................................................................................ 10

Block Diagram ............................................................................................................................. 11

Ball and Pin Assignments .......................................................................................................... 12

Signal Descriptions ..................................................................................................................... 17

Functional Description................................................................................................................ 24

5.1

5.2

Device Overview ................................................................................................................. 24

5.1.1 Comprehensive Functionality ................................................................................ 24

5.1.2 Optimal Signal Processing Architecture.................................................................24

Network Media / Protocol Support ...................................................................................... 25

5.2.1 10/100 Network Interface....................................................................................... 25

5.2.2 MII Data Interface .................................................................................................. 27

5.2.3 Configuration Management Interface .................................................................... 27

Operating Requirements..................................................................................................... 29

5.3.1 Power Requirements ............................................................................................. 29

5.3.2 Clock Requirements ..............................................................................................30

Initialization ......................................................................................................................... 30

5.4.1 MDIO Control Mode and Hardware Control Mode................................................. 31

5.4.2 Reduced-Power Modes ......................................................................................... 32

5.4.3 Reset .....................................................................................................................33

5.4.4 Hardware Configuration Settings ........................................................................... 33

Establishing Link ................................................................................................................. 34

5.5.1 Auto-Negotiation .................................................................................................... 35

5.5.2 Parallel Detection................................................................................................... 36

MII Operation ...................................................................................................................... 36

5.6.1 MII Clocks .............................................................................................................. 37

5.6.2 Transmit Enable..................................................................................................... 39

5.6.3 Receive Data Valid ................................................................................................ 39

5.6.4 Carrier Sense......................................................................................................... 39

5.6.5 Error Signals .......................................................................................................... 40

5.6.6 Collision .................................................................................................................40

5.6.7 Loopback ............................................................................................................... 40

100 Mbps Operation ...........................................................................................................42

5.7.1 100BASE-X Network Operations ........................................................................... 42

5.7.2 Collision Indication ................................................................................................. 44

5.7.3 100BASE-X Protocol Sublayer Operations............................................................ 45

10 Mbps Operation ............................................................................................................. 49

5.8.1 10BASE-T Preamble Handling .............................................................................. 49

5.8.2 10BASE-T Carrier Sense....................................................................................... 49

5.8.3 10BASE-T Dribble Bits .......................................................................................... 49

5.8.4 10BASE-T Link Integrity Test ................................................................................ 50

5.8.5 Link Failure ............................................................................................................ 50

5.8.6 10BASE-T SQE (Heartbeat) .................................................................................. 50

5.8.7 10BASE-T Jabber .................................................................................................. 50

5.3

5.4

5.5

5.6

5.7

5.8

Cortina Systems

LXT971A Single-Port 10/100 Mbps PHY Transceiver

Page 3

LXT971A PHY

Datasheet

249414, Revision 5.2

13 September 2007

Contents

5.9

5.10

5.8.8 10BASE-T Polarity Correction ............................................................................... 50

Monitoring Operations ........................................................................................................ 50

5.9.1 Monitoring Auto-Negotiation .................................................................................. 50

5.9.2 Monitoring Next Page Exchange ........................................................................... 51

5.9.3 LED Functions ....................................................................................................... 51

5.9.4 LED Pulse Stretching............................................................................................. 52

Boundary Scan (JTAG 1149.1) Functions .......................................................................... 52

5.10.1 Boundary Scan Interface ....................................................................................... 52

5.10.2 State Machine ........................................................................................................ 52

5.10.3 Instruction Register ................................................................................................ 53

5.10.4 Boundary Scan Register ........................................................................................ 53

5.10.5 Device ID Register ................................................................................................. 53

Magnetics Information ........................................................................................................ 54

Typical Twisted-Pair Interface ............................................................................................ 54

Fiber Interface..................................................................................................................... 57

DC Electrical Parameters ................................................................................................... 61

AC Timing Diagrams and Parameters ................................................................................ 65

6.0

Application Information .............................................................................................................. 54

6.1

6.2

6.3

7.0

Electrical Specifications ............................................................................................................. 61

7.1

7.2

8.0

9.0

Register Definitions - IEEE Base Registers .............................................................................. 78

10.0 Package Specifications............................................................................................................... 94

Cortina Systems

LXT971A Single-Port 10/100 Mbps PHY Transceiver

Page 4

LXT971A PHY

Datasheet

249414, Revision 5.2

13 September 2007

Figures

Block Diagram ............................................................................................................................... 11

64-Ball PBGA: Ball Assignments .................................................................................................. 13

64-Pin LQFP Package: Pins Assignments ................................................................................... 14

Management Interface Read Frame Structure ............................................................................. 28

Management Interface Write Frame Structure ............................................................................. 28

MII Interrupt Logic ......................................................................................................................... 29

Initialization Sequence .................................................................................................................. 31

Hardware Configuration Settings .................................................................................................. 34

Link Establishment Overview ...................................................................................................... 35

Clocking for 10BASE-T ................................................................................................................. 38

Clocking for 100BASE-X .............................................................................................................. 38

Clocking for Link Down Clock Transition ...................................................................................... 39

Loopback Paths ............................................................................................................................ 41

100BASE-X Frame Format ...........................................................................................................42

100BASE-TX Data Path ............................................................................................................... 43

100BASE-TX Reception with No Errors ....................................................................................... 43

100BASE-TX Reception with Invalid Symbol ............................................................................... 44

100BASE-TX Transmission with No Errors .................................................................................. 44

100BASE-TX Transmission with Collision .................................................................................... 44

Protocol Sublayers ....................................................................................................................... 45

LED Pulse Stretching ................................................................................................................... 52

Typical Twisted-Pair Interface - Switch ......................................................................................... 55

Typical Twisted-Pair Interface - NIC ..............................................................................................56

Typical Media Independent Interface ............................................................................................ 57

Typical Interface - LXT971A PHY to 3.3 V Fiber PHY................................................................... 58

Typical Interface LXT971A PHY to 5 V Fiber PHY........................................................................ 59

Typical Interface - LXT971A PHY to Triple PECL-to-PECL Logic Translator............................... 60

100BASE-TX Receive Timing - 4B Mode ...................................................................................... 66

100BASE-TX Transmit Timing - 4B Mode ..................................................................................... 67

100BASE-FX Receive Timing ....................................................................................................... 68

100BASE-FX Transmit Timing ...................................................................................................... 69

10BASE-T Receive Timing ...........................................................................................................70

10BASE-T Receive Timing ............................................................................................................ 70

10BASE-T Transmit Timing .......................................................................................................... 72

10BASE-T Jabber and Unjabber Timing ...................................................................................... 73

10BASE-T SQE (Heartbeat) Timing ............................................................................................. 73

Auto-Negotiation and Fast Link Pulse Timing ............................................................................... 74

Fast Link Pulse Timing .................................................................................................................. 74

MDIO Input Timing ........................................................................................................................ 75

MDIO Output Timing...................................................................................................................... 75

Power-Up Timing ........................................................................................................................... 76

RESET_L Pulse Width and Recovery Timing ............................................................................... 76

PHY Identifier Bit Mapping ...........................................................................................................81

PBGA Package Specification ........................................................................................................ 94

LQFP Package Specifications ....................................................................................................... 95

Cortina Systems

LXT971A Single-Port 10/100 Mbps PHY Transceiver

Page 5

FLLXT971ABC.A4-834103 Related Products

	FLLXT971ABC.A4-834103	ELLXT971ABC.A4-870477	ELLXT971ABE.A4-870479	FLLXT971ABE.A4-834104	WJLXT971ALC.A4-857342	WJLXT971ALE.A4-857343	ELLXT971ABC.A4-870478	WJLXT971ALE.A4-857346
Description	IC TXRX ETHERNET 100MBPS 64BGA	IC TXRX ETHERNET 100MBPS 64BGA	IC TXRX ETHERNET 100MBPS 64BGA	IC TXRX ETHERNET 100MBPS 64BGA	IC TXRX ETHERNET 100MBPS 64LQFP	IC TXRX ETHERNET 100MBPS 64LQFP	IC TXRX 1/1 ETHERNET 64LFBGA	IC TXRX SDH/SONET/ATM 64LQFP
Is it Rohs certified?	incompatible	conform to	conform to	incompatible	conform to	conform to	conform to	conform to
package instruction	LFBGA, BGA64,8X8,32	LFBGA, BGA64,8X8,32	LFBGA, BGA64,8X8,32	LFBGA, BGA64,8X8,32	LFQFP, QFP64,.47SQ,20	LFQFP, QFP64,.47SQ,20	LFBGA, BGA64,8X8,32	LFQFP, QFP64,.47SQ,20
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
data rate	100000 Mbps	100000 Mbps	100000 Mbps	100000 Mbps	100000 Mbps	100000 Mbps	100000 Mbps	100000 Mbps
JESD-30 code	S-PBGA-B64	S-PBGA-B64	S-PBGA-B64	S-PBGA-B64	S-PQFP-G64	S-PQFP-G64	S-PBGA-B64	S-PQFP-G64
length	7 mm	7 mm	7 mm	7 mm	10 mm	10 mm	7 mm	10 mm
Number of functions	1	1	1	1	1	1	1	1
Number of terminals	64	64	64	64	64	64	64	64
Transceiver quantity	1	1	1	1	1	1	1	1
Maximum operating temperature	70 °C	70 °C	85 °C	85 °C	70 °C	85 °C	70 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA	LFBGA	LFBGA	LFQFP	LFQFP	LFBGA	LFQFP
Encapsulate equivalent code	BGA64,8X8,32	BGA64,8X8,32	BGA64,8X8,32	BGA64,8X8,32	QFP64,.47SQ,20	QFP64,.47SQ,20	BGA64,8X8,32	QFP64,.47SQ,20
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	240	NOT SPECIFIED	260	NOT SPECIFIED	260
power supply	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.36 mm	1.36 mm	1.36 mm	1.36 mm	1.6 mm	1.6 mm	1.36 mm	1.6 mm
Maximum slew rate	0.11 mA	0.11 mA	0.11 mA	0.11 mA	0.11 mA	0.11 mA	0.11 mA	0.11 mA
Nominal supply voltage	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Telecom integrated circuit types	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER	ETHERNET TRANSCEIVER
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL	BALL	GULL WING	GULL WING	BALL	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.5 mm	0.5 mm	0.8 mm	0.5 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	QUAD	QUAD	BOTTOM	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	30	NOT SPECIFIED	40	NOT SPECIFIED	40
width	7 mm	7 mm	7 mm	7 mm	10 mm	10 mm	7 mm	10 mm
Maker	Inphi Corporation	-	-	Inphi Corporation	Inphi Corporation	Inphi Corporation	-	Inphi Corporation
Base Number Matches	-	1	1	1	1	1	1	1

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