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PI74SSTVF16857AEX

Description
IC REGIST BUFF 14BIT DDR 48TSSOP
Categorysemiconductor    logic   
File Size166KB,9 Pages
ManufacturerDiodes
Websitehttp://www.diodes.com/
Environmental Compliance
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PI74SSTVF16857AEX Overview

IC REGIST BUFF 14BIT DDR 48TSSOP

PI74SSTVF16857AEX Parametric

Parameter NameAttribute value
logical typeRegister buffer with SSTL_2 compatible DDR I/O
voltage2.3 V ~ 2.7 V
Number of digits14
Operating temperature0°C ~ 70°C
Installation typesurface mount
Package/casing48-TFSOP (0.240", 6.10mm wide)
Supplier device packaging48-TSSOP
PI74SSTVF16857
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
14-Bit Registered Buffer
Product Features
• PI74 SSTVF16857 is designed for low-voltage operation,
2.5V for PC1600 ~ PC2700; 2.6V for PC3200
• Supports SSTL_2 Class I output specifications
• SSTL_2 Input and Output Levels
• Designed for DDR Memory
• Flow-Through Architecture
• Packaging Options (Pb-free available):
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor’s PI74SSTVF16857 series of logic circuits
are produced using the Company’s advanced sub-micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTVF16857 universal bus driver is designed
for 2.5V to 2.6V V
DD
operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
RESET must be supported with LVCMOS levels as V
REF
may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
Q1
Logic Block Diagram
CLK
CLK
RESET
D1
V
REF
38
39
34
48
35
R
CLK
V
1
D
Pericom’s PI74SSTVF16857 is characterized for operation from
0° to 70°C.
TO 13 OTHER CHANNELS
Product Pin Configuration
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK
CLK
VDD
GND
VREF
RESET
D8
D9
D10
D11
D12
VDD
GND
D13
D14
Product Pin Description
Pin Name
RESET
CLK
CLK
D
Q
GND
V
DD
V
DDQ
V
REF
Description
Reset (Active Low)
Clock Input
Clock Input
Data Input
Data Output
Ground
Core Supply Voltage
Output Supply Voltage
Input Reference Voltage
(1)
48-Pin
39
A, K
38
11
37
36
35
34
33
32
31
30
29
28
27
26
25
Truth Table
RESET
L
H
Η
H
Inputs
CLK
X
L or H
CLK
X
L or H
D
X
H
L
X
Outputs
Q
L
H
L
Q o
( 2 )
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
Notes:
2. Output level before the
1. H = High Signal Level
indicated steady state
L = Low Signal Level
input conditions were
= Transition LOW-to-HIGH
established.
= Transition HIGH-to-LOW
X = Irrelevant
1
PS8656A
05/27/03

PI74SSTVF16857AEX Related Products

PI74SSTVF16857AEX PI74SSTVF16857AE PI74SSTVF16857KE
Description IC REGIST BUFF 14BIT DDR 48TSSOP IC REG BUFFER 14BIT 48TSSOP IC REG BUFFER 14BIT 48TVSOP
logical type Register buffer with SSTL_2 compatible DDR I/O Register buffer with SSTL_2 compatible DDR I/O Register buffer with SSTL_2 compatible DDR I/O
voltage 2.3 V ~ 2.7 V 2.3 V ~ 2.7 V 2.3 V ~ 2.7 V
Number of digits 14 14 14
Operating temperature 0°C ~ 70°C 0°C ~ 70°C 0°C ~ 70°C
Installation type surface mount surface mount surface mount
Package/casing 48-TFSOP (0.240", 6.10mm wide) 48-TFSOP (0.240", 6.10mm wide) 48-TFSOP (0.173", 4.40mm wide)
Supplier device packaging 48-TSSOP 48-TSSOP 48-TVSOP
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