ICS83940-02
L
OW
S
KEW
, 1-
TO
-18
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS83940-02 is a low skew, 1-to-18 Fanout
Buffer and a member of the HiPerClock ™
S
HiPerClockS™
family of High Performance Clock Solutions from
ICS. The 83940-02 has two selectable clock in-
puts. The CLK0, nCLK0 pair can accept most
standard differential input levels. The single ended clock in-
put accepts LVCMOS or LVTTL input levels.The low imped-
ance LVCMOS/LVTTL outputs are designed to drive 50Ω
series or parallel terminated transmission lines. The effective
fanout can be increased from 18 to 36 by utilizing the ability
of the outputs to drive two series terminated lines.
F
EATURES
•
18 LVCMOS/LVTTL outputs, 7Ω typical output impedance
•
Selectable LVCMOS_Clock or CLK0, nCLK0 input pair
•
LVCMOS_CLK supports the following input types:
LVCMOS or LVTTL
•
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Maximum output frequency: 200MHz
•
Output skew: 120ps (maximum)
•
Part-to-part skew: 850ps (maximum)
•
Output supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
•
0°C to 70°C ambient operating temperature
•
Industrial temperature information available upon request
•
Pin compatible with the MPC940L in single supply
applications
ICS
The ICS83940-02 is characterized at full 3.3V, full 2.5V and
mixed 3.3V input and 2.5V output operating supply modes.
Guaranteed output and part-to-part skew characteristics
make the ICS83940 ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_SEL
CLK0
nCLK0
LVCMOS_CLK
P
IN
A
SSIGNMENT
GND
V
DDO
32 31 30 29 28 27 26 25
0
Q0
Q1
Q2
Q3
Q4
Q5
GND
Q0:Q17
GND
LVCMOS_CLK
CLK_SEL
CLK
nCLK
V
DD
V
DDO
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Q17
Q16
Q15
GND
Q14
Q13
Q12
V
DDO
24
23
22
Q6
Q7
Q8
V
DDO
Q9
Q10
Q11
GND
1
ICS83940-02
21
20
19
18
17
32-Lead LQFP
Y Pacakge
7mm x 7mm x 1.4mm package body
Top View
83940AY-02
www.icst.com/products/hiperclocks.html
1
REV. A JULY 30, 2007
ICS83940-02
L
OW
S
KEW
, 1-
TO
-18
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 12, 17, 25
3
4
5
6
7
Name
GND
LVCMOS_CLK
CLK_SEL
CLK0
nCLK0
V
DD
Type
Power
Input
Input
Input
Input
Power
Description
Output supply ground.
Pulldown Clock input. LVCMOS/LVTTL interface levels.
Clock select input. Selects LVCMOS clock input
Pulldown when HIGH. Selects CLK0, nCLK0 inputs when
LOW. LVCMOS/LVTTL itnerface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input
Core supply pin.
Power
Output supply pins.
8, 16, 21, 29
V
DDO
9, 10, 11, 13, 14, Q17, Q16, Q15, Q14, Q13,
15, 18, 19, 20, 22,
Q12, Q11, Q10, Q9, Q8,
Clock outputs. 7
Ω
typical output impedance.
Output
23, 24, 26, 27, 28,
Q7, Q6, Q5, Q4, Q3,
LVCMOS/LVTTL interface levels.
30, 31, 32
Q2, Q1, Q0
NOTE:
Pullup
and
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
5
V
DD
, V
DDO
= 3.465V
V
DD
= 3.465V, V
DDO
= 2.625V
V
DD
, V
DDO
= 2.625V
Test Conditions
Minimum Typical
4
12
18
18
51
51
7
12
Maximum
Units
pF
pF
pF
pF
KΩ
KΩ
Ω
T
ABLE
3A. C
LOCK
S
ELECT
F
UNCTION
T
ABLE
Control Input
CLK_SEL
0
1
CLK0, nCLK0
Selected
De-selected
Clock
LVCMOS_CLK
De-selected
Selected
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
0
0
0
0
0
1
1
LVCMOS_CLK
—
—
—
—
—
—
0
1
CLK0
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
—
—
nCLK0
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
—
—
Outputs
Q0:Q17
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Single Ended
Differential to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Single Ended to Single Ended
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
Inver ting
Inver ting
Non Inver ting
Non Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
83940AY-02
www.icst.com/products/hiperclocks.html
2
REV. A JULY 30, 2007
ICS83940-02
L
OW
S
KEW
, 1-
TO
-18
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
2.5V±5%, V
DDO
= 3V±5%
OR
2.5V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
DD
V
DDO
I
DD
I
DDO
Core Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
3.135
2.375
Typical
3.3
2.5
3.3
2.5
Maximum
3.465
2.625
3.465
2.625
25
25
Units
V
V
V
V
mA
mA
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
2.5V±5%, V
DDO
= 3V±5%
OR
2.5V±5%, T
A
= 0°
TO
70°
Symbol Parameter
V
IH
V
IL
Input High Voltage
Input Low Voltage
LVCMOS_CLK
CLK_SEL
LVCMOS_CLK
CLK_SEL
I
IH
I
IL
V
OH
V
OL
Input High Current
Input Low Current
LVCMOS_CLK,
CLK_SEL
LVCMOS_CLK,
CLK_SEL
V
DD
= V
IN
= 3.465V or
2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DDO
= 3.465V
V
DDO
= 2.625V
V
DDO
= 3.465V or 2.625V
Test Conditions
Minimum
2
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
0.8
150
-5
2.4
1.8
0.5
Units
V
V
V
µA
µA
V
V
V
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See 3.3V Output Load Test Circuit Diagram.
83940AY-02
www.icst.com/products/hiperclocks.html
3
REV. A JULY 30, 2007
ICS83940-02
L
OW
S
KEW
, 1-
TO
-18
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%
OR
2.5V±5%, V
DDO
= 3V±5%
OR
2.5V±5%, T
A
= 0°
TO
70°
Symbol Parameter
I
IH
Input High Current
CLK0
nCLK0
CLK0
I
IL
V
PP
Input Low Current
nCLK0
Test Conditions
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
-5
-150
1.3
V
DD
- 0.85
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.15
Input Common Mode Voltage;
GND + 0.5
V
CMR
NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defined as V
IH
.
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°
TO
70°
Symbol
f
MAX
tp
LH
tp
HL
Parameter
Output Frequency
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
Test Conditions
Minimum Typical
2
2
Maximum
200
3.5
3.5
Units
MHz
ns
ns
ps
ps
ns
ns
%
t
sk(o)
Output Skew; NOTE 2, 4
120
t
sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
850
Output Rise Time
20% to 80%
350
1050
t
R
Output Fall Time
20% to 80%
350
1050
t
F
odc
Output Duty Cycle
f
≤
133MHz
45
55
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages,
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY-02
www.icst.com/products/hiperclocks.html
4
REV. A JULY 30, 2007
ICS83940-02
L
OW
S
KEW
, 1-
TO
-18
D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%; V
DDO
= 2.5V±5%, T
A
= 0°
TO
70°
Symbol
f
MAX
tp
LH
tp
HL
Parameter
Output Frequency
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
Test Conditions
Minimum Typical
2
2
Maximum
200
3.5
3.5
Units
MHz
ns
ns
ps
ps
ns
ns
%
t
sk(o)
Output Skew; NOTE 2, 4
120
t
sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
850
Output Rise Time
20% to 80%
350
1050
t
R
Output Fall Time
20% to 80%
350
1050
t
F
odc
Output Duty Cycle
f
≤
133MHz
45
55
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages,
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5C. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 2.5V±5%, T
A
= 0°
TO
70°
Symbol
f
MAX
tp
LH
tp
HL
Parameter
Output Frequency
Propagation Delay; NOTE 1
Propagation Delay; NOTE 1
Test Conditions
Minimum Typical
2
2
Maximum
200
3.5
3.5
Units
MHz
ns
ns
ps
ps
ns
ns
%
t
sk(o)
Output Skew; NOTE 2, 4
120
t
sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
850
Output Rise Time
20% to 80%
350
1050
t
R
Output Fall Time
20% to 80%
350
1050
t
F
odc
Output Duty Cycle
f
≤
133MHz
40
60
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at V
DDO
/2.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages,
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83940AY-02
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5
REV. A JULY 30, 2007
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