700MHz, Low Jitter, Crystal-to-3.3V
Differential LVPECL Frequency Synthesizer
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES MAY 6, 2017
Data Sheet
84330-02
G
ENERAL
D
ESCRIPTION
The 84330-02 is a general purpose, single
output high frequency synthesizer. The VCO operates
at a frequency range of 250MHz to 700MHz. The VCO
and output frequency can be programmed using the
serial or parallel interfaces to the configuration logic.
The output can be configured to divide the VCO
frequency by 1, 2, 4, and8. Output frequency steps
from 250kHz to 2MHz canbe achiev-ed using a 16MHz
crystal depending on the output divider setting.
F
EATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
Fully integrated PLL, no external loop filter requirements
1 differential 3.3V LVPECL output
Crystal oscillator interface: 10MHz to 25MHz
Output frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
Parallel or serial interface for programming M and N divid-
ers during power-up
RMS Period jitter: 5ps (maximum)
Cycle-to-cycle jitter: 40ps (maximum)
3.3V supply voltage
0°C to 70°C ambient operating temperature
Lead-Free package fully RoHS compliant
Industrial temperature information available upon request
For functional replacement part use 8T49N242
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
©2016 Integrated Device Technology, Inc
1
Revision B May 26, 2016
84330-02 Data Sheet
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes oper-
ation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 6, NOTE 1.
The 84330-02 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A quartz crystal is used as the input to the on-chip oscillator.
The output of the oscillator is divided by 16 prior to the phase
detector. With a 16MHz crystal this provides a 1MHz reference
frequency. The VCO of the PLL operates over a range of 250MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output
of the VCO is scaled by a divider prior to being sent to each of
the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the 84330-02 support two input
modes to program the M divider and N output divider. The two
input operational modes are parallel and serial.
Figure 1
shows
the timing diagram for each mode. In parallel mode the nP_LOAD
input is LOW. The data on inputs M0 through M8 and N0 through
N1 is passed directly to the M divider and N output divider. On
T2
0
0
0
0
1
1
1
1
T1
0
0
1
1
0
0
1
1
T0
0
1
0
1
0
1
0
1
the LOW-to-HIGH transition of the nP_LOAD input, the data is
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. The TEST
output is Mode 000 (shift register out) when operating in the par-
allel input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fxtal x
fVCO =
2M
16
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are de-
fined as 125
≤
M
≤
350. The frequency out is defined as follows:
fout = fVCO = fxtal x 2M
N
N
16
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider when S_LOAD transitions
from LOW-to-HIGH. The M divide and N output divide values are
latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD
is held HIGH, data at the S_DATA input is passed directly to the
M divider on each rising edge of S_CLOCK. The serial mode
can be used to program the M and N bits and test bits T2:T0.
The internal registers T2:T0 determine the state of the TEST
output as follows:
TEST Output
Shift Register Out
High
PLL Reference Xtal ÷ 16
(VCO ÷ M) /2 (non 50% Duty Cycle M divider)
fOUT
LVCMOS Output Frequency < 200MHz
Low
(S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider)
fOUT ÷ 4
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
fOUT
S_CLOCK ÷ N divider
fOUT
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
NOTE: nP_LOAD is designed to eliminate runt pulses when changing M and N bits.
©2016 Integrated Device Technology, Inc
2
Revision B May 26, 2016
84330-02 Data Sheet
T
ABLE
1. P
IN
D
ESCRIPTIONS
Name
V
CCA
XTAL_IN,
XTALOUT
XTAL_SEL
OE
nP_LOAD
M0, M1, M2
M3, M4, M5
M6, M7, M8
N0, N1
V
EE
TEST
V
CC
nFOUT, FOUT
nc
FREF_EXT
S_CLOCK
S_DATA
S_LOAD
Input
Input
Input
Pullup
Pullup
Pullup
Power
Type
Description
Analog supply pin.
Crystal oscillator interface. XTAL_IN is an oscillator input.
XTAL_OUT is an oscillator output.
Selects between the crystal oscillator or FREF_EXT inputs as the PLL reference
source. Selects XTAL inputs when HIGH. Selects FREF_EXT when LOW.
LVCMOS / LVTTL interface levels.
Output enable. LVCMOS / LVTTL interface levels.
Parallel load input. Determines when data present at M8:M0 is loaded into
M divider, and when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVC-
MOS / LVTTL interface levels.
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
Negative supply pins.
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
Core supply pins.
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Do not connect.
Pulldown PLL reference input. LVCMOS / LVTTL interface levels.
Clocks the serial data present at S_DATA input into the shift register on the
Pulldown
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
Pulldown
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
Pulldown
LVCMOS / LVTTL interface levels.
Input
Input
Power
Output
Power
Output
Unused
Input
Input
Input
Input
Pullup
Pullup
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
©2016 Integrated Device Technology, Inc
3
Revision B May 26, 2016
84330-02 Data Sheet
T
ABLE
3A. P
ARALLEL AND
S
ERIAL
M
ODE
F
UNCTION
T
ABLE
Inputs
nP_LOAD
L
↑
H
H
H
H
H
M
Data
Data
X
X
X
X
X
N
Data
Data
X
X
X
X
X
S_LOAD
X
L
L
↑
↓
L
H
S_CLOCK
X
X
↑
L
L
X
S_DATA
X
X
Data
Data
Data
X
Data
Conditions
Data on M and N inputs passed directly to M divider and N
output divider. TEST mode 000.
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
M divide and N output divide values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑
= Rising edge transition
↓
= Falling edge transition
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
VCO Frequency
(MHz)
250
252
254
256
•
•
696
698
700
M Divide
125
126
127
128
•
•
348
349
350
256
M8
0
0
0
0
•
•
1
1
1
128
M7
0
0
0
1
•
•
0
0
0
64
M6
1
1
1
0
•
•
1
1
1
32
M5
1
1
1
0
•
•
0
0
0
16
M4
1
1
1
0
•
•
1
1
1
8
M3
1
1
1
0
•
•
1
1
1
4
M2
1
1
1
0
•
•
1
1
1
2
M1
0
1
1
0
•
•
0
0
1
1
M0
1
0
1
0
•
•
0
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
T
ABLE
3C. P
ROGRAMMABLE
O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
Inputs
N1
0
0
1
1
N0
0
1
0
1
N Divider Value
2
4
8
1
Output Frequency (MHz)
Minimum
125
62.5
31.25
250
Maximum
350
175
87.5
700
©2016 Integrated Device Technology, Inc
4
Revision B May 26, 2016
84330-02 Data Sheet
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5 V
50mA
100mA
37.8°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions
beyond those listed in the
DC Characteristics
or
AC Charac-
teristics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. DC P
OWER
S
UPPLY
C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
I
CC
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
130
15
Units
V
V
mA
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
Input Low Voltage
M0-M8, N0, N1,
OE, nP_LOAD, XTAL_
SEL
Input High Current
S_LOAD, S_CLOCK
FREF_EXT, S_DATA
M0-M8, N0, N1,
OE, nP_LOAD, XTAL_
SEL
Input Low Current
S_LOAD, S_CLOCK
FREF_EXT, S_DATA
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
2.6
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
I
IH
I
IL
V
OH
V
OL
NOTE 1: Outputs terminated with 50Ω to V
CC
/2.
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50Ω to V
CC
- 2V.
©2016 Integrated Device Technology, Inc
5
Revision B May 26, 2016
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